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PIC16F7X
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
* PIC16F73 * PIC16F74 * PIC16F76 * PIC16F77
Pin Diagram PDIP
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
Microcontroller Core Features:
* High-performance RISC CPU * Only 35 single word instructions to learn * All single cycle instructions except for program branches which are two cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle * Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) * Pinout compatible to the PIC16C73B/74B/76/77 * Pinout compatible to the PIC16F873/874/876/877 * Interrupt capability (up to 12 sources) * Eight level deep hardware stack * Direct, Indirect and Relative Addressing modes * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code protection * Power saving SLEEP mode * Selectable oscillator options * Low power, high speed CMOS FLASH technology * Fully static design * In-Circuit Serial Programming (ICSP) via two pins * Processor read access to program memory * Wide operating voltage range: 2.0V to 5.5V * High Sink/Source Current: 25 mA * Industrial temperature range * Low power consumption: - < 2 mA typical @ 5V, 4 MHz - 20 A typical @ 3V, 32 kHz - < 1 A typical standby current
Peripheral Features:
* Timer0: 8-bit timer/counter with 8-bit prescaler * Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Two Capture, Compare, PWM modules - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit * 8-bit multi-channel Analog-to-Digital converter * Synchronous Serial Port (SSP) with SPI (Master mode) and I2C (Slave) * Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) * Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only) * Brown-out detection circuitry for Brown-out Reset (BOR)
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Advance Information
PIC16F77/74
DS30325A-page 1
PIC16F7X
Pin Diagrams DIP, SOIC, SSOP
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
PIC16F76/73
PLCC
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC
QFP
44 43 42 41 40 39 38 37 36 35 34
NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3
1 2 3 4 5 6 7 8 9 10 11
PIC16F77 PIC16F74
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS RA4/T0CKI
DS30325A-page 2
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RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC
18 19 20 21 22 23 24 25 26 27 282
RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CK1 NC
6 5 4 3 2 1 44 43 42 41 40
RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC 39 38 37 36 35 34 33 32 31 30 9
7 8 9 10 11 12 13 14 15 16 17
PIC16F77 PIC16F74
RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT
2000 Microchip Technology Inc.
PIC16F7X
Key Features PICmicroTM Mid-Range Reference Manual (DS33023)
PIC16F73
PIC16F74
PIC16F76
PIC16F77
Operating Frequency RESETS (and Delays) FLASH Program Memory (14-bit words, 100 E/W cycles) Data Memory (bytes) Interrupts I/O Ports Timers Capture/Compare/PWM Modules Serial Communications Parallel Communications 8-bit Analog-to-Digital Module Instruction Set
DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 11 Ports A,B,C 3 2 SSP, USART -- 35 Instructions
DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 12 Ports A,B,C,D,E 3 2 SSP, USART PSP 35 Instructions
DC - 20 MHz POR, BOR (PWRT, OST) 8K 368 11 Ports A,B,C 3 2 SSP, USART -- 35 Instructions
DC - 20 MHz POR, BOR (PWRT, OST) 8K 368 12 Ports A,B,C,D,E 3 2 SSP, USART PSP 35 Instructions
5 Input Channels 8 Input Channels 5 Input Channels 8 Input Channels
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DS30325A-page 3
PIC16F7X
Table of Contents
1.0 Device Overview ............................................................................................................................................................ 5 2.0 Memory Organization .................................................................................................................................................. 11 3.0 I/O Ports....................................................................................................................................................................... 29 4.0 Reading Program Memory........................................................................................................................................... 41 5.0 Timer0 Module ............................................................................................................................................................. 45 6.0 Timer1 Module ............................................................................................................................................................. 49 7.0 Timer2 Module ............................................................................................................................................................. 53 8.0 Capture/Compare/PWM Modules ................................................................................................................................ 55 9.0 Synchronous Serial Port (SSP) Module....................................................................................................................... 61 10.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ...................................................................... 73 11.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................... 89 12.0 Special Features of the CPU ....................................................................................................................................... 95 13.0 Instruction Set Summary ........................................................................................................................................... 111 14.0 Development Support ................................................................................................................................................ 119 15.0 Electrical Characteristics ........................................................................................................................................... 125 16.0 DC and AC Characteristics Graphs and Tables ........................................................................................................ 147 17.0 Packaging Information ............................................................................................................................................... 149 Appendix A: Revision History ......................................................................................................................................................... 157 Appendix B: Device Differences..................................................................................................................................................... 157 Appendix C: Conversion Considerations ....................................................................................................................................... 157 Index .................................................................................................................................................................................................. 159 On-Line Support................................................................................................................................................................................. 165 Reader Response .............................................................................................................................................................................. 166 PIC16F7X Product Identification System ........................................................................................................................................... 167
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DS30325A-page 4
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PIC16F7X
1.0 DEVICE OVERVIEW
This document contains device specific information. Additional information may be found in the PICmicroTM Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. There are four devices (PIC16F73, PIC16F74, PIC16F76 and PIC16F77) covered by this data sheet. The PIC16F76/73 devices are available in 28-pin packages and the PIC16F77/74 devices are available in 40-pin packages. The 28-pin devices do not have a Parallel Slave Port implemented. The following two figures are device block diagrams sorted by pin number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2. The 28-pin and 40-pin pinouts are listed in Table 1-1 and Table 1-2, respectively.
FIGURE 1-1:
Device PIC16F73 PIC16F76
PIC16F73 AND PIC16F76 BLOCK DIAGRAM
Program FLASH 4K 8K Data Memory 192 Bytes 368 Bytes
13 Program Counter FLASH Program Memory 8 Level Stack (13-bit) Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/ RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
RAM File Registers
Program Bus
14 Instruction reg Direct Addr 7
RAM Addr (1)
9
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8 3 PORTC
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
W reg
MCLR
VDD, VSS
Timer0
Timer1
Timer2
8-bit A/D
CCP1,2
Synchronous Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
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DS30325A-page 5
PIC16F7X
FIGURE 1-2:
Device PIC16F74 PIC16F77
PIC16F74 AND PIC16F77 BLOCK DIAGRAM
Program FLASH 4K 8K Data Memory 192 Bytes 368 Bytes
13 Program Counter FLASH Program Memory 8 Level Stack (13-bit) Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC 3 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD W reg RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS
RAM File Registers
Program Bus
14 Instruction reg Direct Addr 7
RAM Addr (1)
9
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
Parallel Slave Port MCLR VDD, VSS
Timer0
Timer1
Timer2
8-bit A/D
CCP1,2
Synchronous Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
DS30325A-page 6
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2000 Microchip Technology Inc.
PIC16F7X
TABLE 1-1:
Pin Name
OSC1/CLKIN OSC2/CLKOUT
PIC16F73 AND PIC16F76 PINOUT DESCRIPTION
DIP Pin#
9 10
SSOP SOIC Pin#
9 10
I/O/P Type
I O
Buffer Type
Description
ST/CMOS(3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (RESET) input or programming voltage input or High Voltage Test mode control. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0. RA1 can also be analog input1. RA2 can also be analog input2. RA3 can also be analog input3 or analog reference voltage. RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
MCLR/VPP
1
1
I/P
ST
RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4
2 3 4 5 6 7
2 3 4 5 6 7
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7
21 22 23 24 25 26 27 28
21 22 23 24 25 26 27 28
I/O I/O I/O I/O I/O I/O I/O I/O
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST ST ST ST ST ST ST ST ST --
--
(2)
RB0 can also be the external interrupt pin.
Interrupt-on-change pin. Interrupt-on-change pin. Interrupt-on-change pin or Serial programming clock. Interrupt-on-change pin or Serial programming data. PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT VSS VDD Legend: I = input
11 12 13 14 15 16 17 18 8, 19
20
11 12 13 14 15 16 17 18 8, 19
20
I/O I/O I/O I/O I/O I/O I/O I/O P
P
RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1 can also be the Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode). RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7 can also be the USART Asynchronous Receive or Synchronous Data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 7
PIC16F7X
TABLE 1-2:
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16F74 AND PIC16F77 PINOUT DESCRIPTION
DIP Pin# 13 14 PLCC Pin# 14 15 QFP Pin# 30 31 I/O/P Type I O Buffer Type ST/CMOS(4) -- Description Oscillator crystal input/external clock source input. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (RESET) input or programming voltage input or High Voltage Test mode control. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0. RA1 can also be analog input1. RA2 can also be analog input2. RA3 can also be analog input3 or analog reference voltage. RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
MCLR/VPP
1
2
18
I/P
ST
RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4
2 3 4 5 6 7
3 4 5 6 7 8
19 20 21 22 23 24
I/O I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST TTL
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7
33 34 35 36 37 38 39 40
36 37 38 39 41 42 43 44
8 9 10 11 14 15 16 17
I/O I/O I/O I/O I/O I/O I/O I/O
TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST ST ST ST ST ST ST ST ST
(2)
RB0 can also be the external interrupt pin.
Interrupt-on-change pin. Interrupt-on-change pin. Interrupt-on-change pin or Serial programming clock. Interrupt-on-change pin or Serial programming data. PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT Legend: I = input
15 16 17 18 23 24 25 26
16 18 19 20 25 26 27 29
32 35 36 37 42 43 44 1
I/O I/O I/O I/O I/O I/O I/O I/O
RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode). RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7 can also be the USART Asynchronous Receive or Synchronous Data. P = power ST = Schmitt Trigger input
O = output -- = Not used
I/O = input/output TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS30325A-page 8
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2000 Microchip Technology Inc.
PIC16F7X
TABLE 1-2:
Pin Name
PIC16F74 AND PIC16F77 PINOUT DESCRIPTION (CONTINUED)
DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus.
RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7
19 20 21 22 27 28 29 30
21 22 23 24 30 31 32 33
38 39 40 41 2 3 4 5
I/O I/O I/O I/O I/O I/O I/O I/O
ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3)
PORTE is a bi-directional I/O port. RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VSS VDD NC Legend: I = input
8 9 10 12,31 11,32 -- 9 10 11 13,34 12,35 1,17,28, 40 25 26 27 6,29 7,28 12,13, 33,34 I/O I/O I/O P P ST/TTL(3) ST/TTL(3) ST/TTL(3) -- -- --
RE0 can also be read control for the parallel slave port, or analog input5. RE1 can also be write control for the parallel slave port, or analog input6. RE2 can also be select control for the parallel slave port, or analog input7. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. These pins are not internally connected. These pins should be left unconnected. P = power ST = Schmitt Trigger input
O = output -- = Not used
I/O = input/output TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
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DS30325A-page 9
PIC16F7X
NOTES:
DS30325A-page 10
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PIC16F7X
2.0 MEMORY ORGANIZATION
FIGURE 2-2:
There are two memory blocks in each of these PICmicro(R) MCUs. The Program Memory and Data Memory have separate buses so that concurrent access can occur and is detailed in this section. The Program Memory can be read internally by user code (see Section 4.0). Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual, (DS33023).
PIC16F74/73 PROGRAM MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2
2.1
Program Memory Organization
Stack Level 8
The PIC16F7X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F77/76 devices have 8K x 14 words of FLASH program memory and the PIC16F73/74 devices have 4K x 14. Accessing a location above the physically implemented address will cause a wraparound. The RESET Vector is at 0000h and the Interrupt Vector is at 0004h.
RESET Vector
0000h
Interrupt Vector
0004h 0005h
FIGURE 2-1:
PIC16F77/76 PROGRAM MEMORY MAP AND STACK
PC<12:0>
On-Chip Program Memory
Page 0
07FFh 0800h
Page 1
0FFFh 1000h
CALL, RETURN RETFIE, RETLW
13
1FFFh
Stack Level 1 Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h 0005h
Page 0
07FFh 0800h
Page 1 On-Chip Program Memory Page 2
17FFh 1800h 0FFFh 1000h
Page 3
1FFFh
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DS30325A-page 11
PIC16F7X
2.2 Data Memory Organization
The Data Memory is partitioned into multiple banks, which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. RP1:RP0 00 01 10 11 Bank 0 1 2 3
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly, through the File Select Register FSR.
DS30325A-page 12
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PIC16F7X
FIGURE 2-3: PIC16F77/76 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(*) 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h TRISB 86h TRISC 87h TRISD(1) 88h TRISE(1) 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch PIE2 8Dh PCON 8Eh 8Fh 90h 91h PR2 92h SSPADD 93h SSPSTAT 94h 95h 96h 97h 98h TXSTA 99h SPBRG 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh ADCON1 A0h General Purpose Register 80 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch PMDATA PMADR 10Dh 10Eh PMDATH 10Fh PMADRH 110h 111h 112h 113h 114h 115h 116h General 117h Purpose 118h Register 119h 16 Bytes 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON PMCON1
General Purpose Register 16 Bytes
General Purpose Register 96 Bytes
EFh F0h FFh
General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2
16Fh 170h 17Fh
General Purpose Register 80 Bytes accesses 70h - 7Fh Bank 3
1EFh 1F0h 1FFh
Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are not implemented on 28-pin devices.
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DS30325A-page 13
PIC16F7X
FIGURE 2-4: PIC16F74/73 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(*) 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h TRISB 86h TRISC 87h TRISD(1) 88h TRISE(1) 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch PIE2 8Dh PCON 8Eh 8Fh 90h 91h PR2 92h SSPADD 93h SSPSTAT 94h 95h 96h 97h 98h TXSTA 99h SPBRG 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh ADCON1 A0h General Purpose Register 96 Bytes File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch PMDATA PMADR 10Dh 10Eh PMDATH 10Fh PMADRH 110h File Address Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h
PCLATH INTCON PMCON1
120h
1A0h
General Purpose Register 96 Bytes
accesses 20h-7Fh 16Fh 170h FFh 17Fh Bank 2
accesses A0h - FFh 1EFh 1F0h 1FFh Bank 3
7Fh Bank 0 Bank 1
Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are not implemented on 28-pin devices.
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2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section.
TABLE 2-1:
Address Bank 0 00h(4) 01h 02h(4) 03h(4) 04h(4) 05h 06h 07h 08h(5) 09h(5) 0Ah(1,4) 0Bh(4) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: 3: 4: 5: 6: INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS(2)
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --0x 0000 xxxx xxxx xxxx xxxx xxxx xxxx
0000 0000 uuuu uuuu 0000 0000 000q quuu uuuu uuuu --0u 0000 uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu ---0 0000 0000 000u 0000 0000 ---- ---0 uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 -000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0000 0000 -00x 0000 0000 0000 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu 0000 00-0
Indirect data memory address pointer -- -- PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read -- -- GIE PSPIF(3) -- -- -- PEIE ADIF -- -- -- T0IE RCIF -- -- -- RE2 RE1 RE0
---- -xxx ---0 0000 0000 000x 0000 0000 ---- ---0 xxxx xxxx xxxx xxxx
Write Buffer for the upper 5 bits of the Program Counter INTE TXIF -- RBIE SSPIF -- T0IF CCP1IF -- INTF TMR2IF -- RBIF TMR1IF CCP2IF
Holding register for the Least Significant Byte of the 16-bit TMR1 Register Holding register for the Most Significant Byte of the 16-bit TMR1 Register -- -- WCOL -- T1CKPS1 T1CKPS0 TOUTPS CKP T1OSCEN T1SYNC TMR1CS TMR1ON Timer2 Module's Register TOUTPS3 TOUTPS2 SSPOV SSPEN Synchronous Serial Port Receive Buffer/Transmit Register SSPM3 SSPM2 SSPM1 SSPM0 Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- SPEN -- RX9 CCP1X SREN CCP1Y CREN CCP1M3 -- CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D
--00 0000 0000 0000
TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 -00x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx
CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0
USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) -- -- CCP2X CCP2Y CCP2M3 CCP2M2 GO/ DONE CCP2M1 CCP2M0 A/D Result Register Byte ADCS1 ADCS0 CHS2 CHS1 CHS0 -- ADON
--00 0000 xxxx xxxx 0000 00-0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as `0'. This bit always reads as a `1'.
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TABLE 2-1:
Address Bank 1 80h(4) 81h 82h(4) 83h(4) 84h(4) 85h 86h 87h 88h(5) 89h(5) 8Ah(1,4) 8Bh(4) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: 2: 3: 4: 5: 6: INDF OPTION_ REG PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON -- -- -- PR2 SSPADD SSPSTAT -- -- -- TXSTA SPBRG -- -- -- -- -- ADCON1 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 000q quuu uuuu uuuu --11 1111 1111 1111 1111 1111 1111 1111 0000 -111 ---0 0000 0000 000u 0000 0000 ---- ---0 ---- --uu -- -- -- 1111 1111 0000 0000 0000 0000 -- -- -- 0000 -010 0000 0000 -- -- -- -- -- ---- -000
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS(2)
Name
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0001 1xxx xxxx xxxx --11 1111 1111 1111 1111 1111 1111 1111
Indirect data memory address pointer -- -- PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF -- GIE PSPIE(3) -- -- OBF -- PEIE ADIE -- -- IBOV -- T0IE RCIE -- -- PSPMODE -- PORTE Data Direction Bits
0000 -111 ---0 0000 0000 000x 0000 0000 ---- ---0 ---- --qq -- -- -- 1111 1111 0000 0000
Write Buffer for the upper 5 bits of the Program Counter INTE TXIE -- -- RBIE SSPIE -- -- T0IF CCP1IE -- -- INTF TMR2IE -- POR RBIF TMR1IE CCP2IE BOR
Unimplemented Unimplemented Unimplemented Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S R/W UA BF Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D Baud Rate Generator Register Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- -- PCFG2 PCFG1 PCFG0
0000 0000 -- -- -- 0000 -010 0000 0000 -- -- -- -- -- ---- -000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as `0'. This bit always reads as a `1'.
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TABLE 2-1:
Address Bank 2 100h(4) 101h 102h(4) 103h(4) 104h(4) 105h 106h 107h 108h 109h 10Bh(4) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(4) 181h 182h(4) 183h(4) 184h(4) 185h 186h 187h 188h 189h 18Bh(4) 18Ch 18Dh 18Eh 18Fh Legend: Note 1: 2: 3: 4: 5: 6: INDF OPTION_ REG PCL STATUS FSR -- TRISB -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 000q quuu uuuu uuuu -- 1111 1111 -- -- -- ---0 0000 0000 000u 1--- ---0 -- 0000 0000 0000 0000
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS(2)
Name
INDF TMR0 PCL STATUS FSR -- PORTB -- -- --
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx -- xxxx xxxx -- -- --
0000 0000 uuuu uuuu 0000 0000 000q quuu uuuu uuuu -- uuuu uuuu -- -- -- ---0 0000 0000 000u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Indirect Data Memory Address Pointer Unimplemented PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented Unimplemented -- GIE -- PEIE -- T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF
10Ah(1,4) PCLATH INTCON PMDATA PMADR PMDATH PMADRH
---0 0000 0000 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Data Register Low Byte Address Register Low Byte -- -- -- -- Data Register High Byte -- Address Register High Byte
Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0001 1xxx xxxx xxxx -- 1111 1111 -- -- --
Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE -- (6) -- PEIE -- -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE -- T0IF -- INTF -- RBIF RD
18Ah(1,4) PCLATH INTCON PMCON1 -- -- --
---0 0000 0000 000x 1--- ---0 -- 0000 0000 0000 0000
Unimplemented Reserved maintain clear Reserved maintain clear
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as `0'. This bit always reads as a `1'.
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2.2.2.1 STATUS Register The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, or DC bits from the STATUS register. For other instructions not affecting any status bits, see the "Instruction Set Summary." Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 IRP bit 7 bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction
Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero
R/W-0 RP1
R/W-0 RP0
R-1 TO
R-1 PD
R/W-x Z
R/W-x DC
R/W-x C bit 0
bit 6-5
bit 4
bit 3
bit 2
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 0
Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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2.2.2.2 OPTION_REG Register Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 RBPU bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits
Bit Value
000 001 010 011 100 101 110 111
R/W-1 INTEDG
R/W-1 T0CS
R/W-1 T0SE
R/W-1 PSA
R/W-1 PS2
R/W-1 PS1
R/W-1 PS0 bit 0
bit 6
bit 5
bit 4
bit 3
bit 2-0
TMR0 Rate
1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
WDT Rate
1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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2.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 GIE bit 7 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.2.2.4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the individual enable bits for the peripheral interrupts.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 PSPIE bit 7 bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear. Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
(1)
R/W-0 ADIE
R/W-0 RCIE
R/W-0 TXIE
R/W-0 SSPIE
R/W-0 CCP1IE
R/W-0 TMR2IE
R/W-0 TMR1IE bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.2.2.5 PIR1 Register Note: The PIR1 register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 PSPIF(1) bit 7 bit 7 PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag 1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are: SPI A transmission/reception has taken place. I2 C Slave A transmission/reception has taken place. I2 C Master A transmission/reception has taken place. The initiated START condition was completed by the SSP module. The initiated STOP condition was completed by the SSP module. The initiated Restart condition was completed by the SSP module. The initiated Acknowledge condition was completed by the SSP module. A START condition occurred while the SSP module was idle (Multi-master system). A STOP condition occurred while the SSP module was idle (Multi-master system). 0 = No SSP interrupt condition has occurred. CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: PSPIF is reserved on 28-pin devices; always maintain this bit clear. Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0 -- bit 7 bit 7-1 bit 0 Unimplemented: Read as '0' CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CCP2IE bit 0
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2.2.2.7 PIR2 Register
.
The PIR2 register contains the flag bits for the CCP2 interrupt.
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0 -- bit 7 bit 7-1 bit 0 Unimplemented: Read as '0' CCP2IF: CCP2 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CCP2IF bit 0
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2.2.2.8 PCON Register Note: The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don't care and is not predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the configuration word).
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
U-0 -- bit 7 bit 7-2 bit 1 Unimplemented: Read as '0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-1 BOR bit 0
bit 0
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PIC16F7X
2.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.
2.4
Program Memory Paging
FIGURE 2-5:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0 Instruction with PCL as Destination ALU
PCH 12 PC 5
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0
GOTO,CALL
PIC16F7X devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack). Note: The contents of the PCLATH are unchanged after a RETURN or RETFIE instruction is executed. The user must setup the PCLATH for any subsequent CALLS or GOTOS.
2.3.1
COMPUTED GOTO
Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used).
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note, "Implementing a Table Read" (AN556). 2.3.2 STACK
EXAMPLE 2-1:
ORG 0x500 BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1 : : : RETURN
CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0
;Select page 1 (800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to Call subroutine ;in page 0 (000h-7FFh)
The PIC16F7X family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
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2.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-2:
movlw movwf clrf incf btfss goto :
INDIRECT ADDRESSING
0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-6. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
NEXT
CONTINUE
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing 0 IRP 7 FSR register 0
RP1:RP0
6
from opcode
bank select
location select 00 00h 01 80h 10 100h 11 180h
bank select
location select
Data Memory(1)
7Fh Bank 0 Note 1:
FFh Bank 1
17Fh Bank 2
1FFh Bank 3
For register file map detail see Figure 2-3.
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NOTES:
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3.0 I/O PORTS
FIGURE 3-1:
Data Bus
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS
Q VDD
D
WR Port
CK
Q
P
Data Latch
3.1
PORTA and the TRISA Register
WR TRIS
D
Q
N
I/O pin(1)
PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other PORTA pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
CK
Q Analog Input Mode
VSS
TRIS Latch
RD TRIS
TTL Input Buffer D
Q
EN
RD PORT
To A/D Converter Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 3-2:
Data Bus WR PORT
BLOCK DIAGRAM OF RA4/ T0CKI PIN
D Q Q N Data Latch D Q Q VSS Schmitt Trigger Input Buffer
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set, when using them as analog inputs.
CK
I/O pin(1)
EXAMPLE 3-1:
BCF BCF CLRF
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Bank0 Initialize PORTA by clearing output data latches Select Bank 1 Configure all pins as digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6> are always read as '0'.
WR TRIS
STATUS, RP0 STATUS, RP1 PORTA
CK
TRIS Latch
BSF MOVLW MOVWF MOVLW
STATUS, RP0 0x06 ADCON1 0xCF
RD TRIS Q D EN EN RD PORT
MOVWF
TRISA
TMR0 clock input Note 1: I/O pin has protection diodes to VSS only.
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PIC16F7X
TABLE 3-1:
Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4
PORTA FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 Buffer TTL TTL TTL TTL ST TTL Input/output or analog input. Input/output or analog input. Input/output or analog input. Input/output or analog input or VREF. Input/output or external clock input for Timer0. Output is open drain type. Input/output or slave select input for synchronous serial port or analog input. Function
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2:
Address 05h 85h 9Fh
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 RA5 -- Bit 4 RA4 -- Bit 3 RA3 -- Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on: Value on all POR, other BOR RESETS
--0x 0000 --11 1111 --0u 0000 --11 1111 ---- -000
PORTA TRISA ADCON1
PORTA Data Direction Register
PCFG2 PCFG1 PCFG0 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note:
When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of the following modes where PCFG2:PCFG0 = 100, 101, 11x.
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3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. This interrupt on mismatch feature, together with software configureable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. Refer to the Embedded Control Handbook, "Implementing Wake-Up on Key Stroke" (AN552). RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG<6>).
FIGURE 3-3:
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD Weak P Pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
RBPU(2)
Data Bus WR Port
RB0/INT is discussed in detail in Section 12.10.1.
WR TRIS
CK
TTL Input Buffer
FIGURE 3-4:
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD Weak P Pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
RBPU(2) RD TRIS Q RD Port D EN WR Port
Data Bus
RB0/INT Schmitt Trigger Buffer Note 1: 2: RD Port WR TRIS
CK
TTL Input Buffer
ST Buffer
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
RD TRIS Q
Latch D EN Q1
Four of PORTB's pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
RD Port Set RBIF
From other RB7:RB4 pins
Q
D RD Port EN Q3
RB7:RB6 in Serial Programming mode Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
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TABLE 3-3:
Name RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7
PORTB FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 3-4:
Address 06h, 106h 86h, 186h 81h, 181h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on: POR, BOR Value on all other RESETS
PORTB TRISB OPTION_REG
xxxx xxxx uuuu uuuu 1111 1111 1111 1111
PORTB Data Direction Register RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
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3.3 PORTC and the TRISC Register FIGURE 3-5:
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Port/Peripheral Select(2) Peripheral Data Out Data Bus WR Port 0 D CK Q 1 Q VDD P
Data Latch WR TRIS D CK Q Q N VSS RD TRIS Peripheral OE(3) RD Port Peripheral Input Note 1: 2: 3: I/O pins have diode protection to VDD and VSS. Port/Peripheral select signal selects between port data and peripheral output. Peripheral OE (output enable) is only activated if peripheral select is active. Q D EN Schmitt Trigger I/O pin(1)
TRIS Latch
TABLE 3-5:
Name
PORTC FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. Input/output port pin or Capture1 input/Compare1 output/PWM1 output. RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output. Input/output port pin or USART Asynchronous Transmit or Synchronous Clock. Input/output port pin or USART Asynchronous Receive or Synchronous Data.
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
Legend: ST = Schmitt Trigger input
TABLE 3-6:
Address 07h 87h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on: POR, BOR
xxxx xxxx 1111 1111
Name PORTC TRISC
Value on all other RESETS
uuuu uuuu 1111 1111
PORTC Data Direction Register
Legend: x = unknown, u = unchanged
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3.4 PORTD and TRISD Registers FIGURE 3-6:
Data Bus WR Port
This section is not applicable to the PIC16F73 or PIC16F76. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configureable as an input or output. PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
PORTD BLOCK DIAGRAM (IN I/O PORT MODE)
D Q I/O pin(1) CK
Data Latch D WR TRIS Q Schmitt Trigger Input Buffer
CK TRIS Latch
RD TRIS Q D EN EN RD Port Note 1: I/O pins have protection diodes to Vdd and Vss.
TABLE 3-7:
Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7
PORTD FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) Function Input/output port pin or parallel slave port bit0 Input/output port pin or parallel slave port bit1 Input/output port pin or parallel slave port bit2 Input/output port pin or parallel slave port bit3 Input/output port pin or parallel slave port bit4 Input/output port pin or parallel slave port bit5 Input/output port pin or parallel slave port bit6 Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.
TABLE 3-8:
Address 08h 88h 89h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit 7 RD7 IBF Bit 6 RD6 OBF Bit 5 RD5 IBOV Bit 4 RD4 PSPMODE Bit 3 RD3 -- Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on: POR, BOR
xxxx xxxx 1111 1111 0000 -111
Value on all other RESETS
uuuu uuuu 1111 1111 0000 -111
PORTD TRISD TRISE
PORTD Data Direction Register PORTE Data Direction bits
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
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3.5 PORTE and TRISE Register FIGURE 3-7:
Data Bus WR PORT
This section is not applicable to the PIC16F73 or PIC16F76. PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configureable as inputs or outputs. These pins have Schmitt Trigger input buffers. I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs). Ensure ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL. Register 3-1 shows the TRISE register, which also controls the parallel slave port operation. PORTE pins are multiplexed with analog inputs. When selected as an analog input, these pins will read as '0's. TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, these pins are configured as analog inputs and read as `0'.
PORTE BLOCK DIAGRAM (IN I/O PORT MODE)
D Q I/O pin(1) CK
Data Latch D WR TRIS Q Schmitt Trigger Input Buffer
CK TRIS Latch
RD TRIS Q D EN EN RD PORT Note 1: I/O pins have protection diodes to Vdd and Vss.
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REGISTER 3-1: TRISE REGISTER (ADDRESS 89h)
R-0 IBF bit 7 bit 7 Parallel Slave Port Status/Control Bits IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode Unimplemented: Read as '0' PORTE Data Direction Bits Bit2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 -- R/W-1 bit2 R/W-1 bit1 R/W-1 bit0 bit 0
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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TABLE 3-9:
Name RE0/RD/AN5
PORTE FUNCTIONS
Bit# bit0 Buffer Type ST/TTL(1) Function Input/output port pin or read control input in Parallel Slave Port mode or analog input: RD 1 = Idle 0 = Read operation. Contents of PORTD register output to PORTD I/O pins (if chip selected). Input/output port pin or write control input in Parallel Slave Port mode or analog input: WR 1 = Idle 0 = Write operation. Value of PORTD I/O pins latched into PORTD register (if chip selected). Input/output port pin or chip select control input in Parallel Slave Port mode or analog input: CS 1 = Device is not selected 0 = Device is selected
RE1/WR/AN6
bit1
ST/TTL(1)
RE2/CS/AN7
bit2
ST/TTL(1)
Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 3-10:
Addr 09h 89h 9Fh Name PORTE TRISE ADCON1
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7 -- IBF -- Bit 6 -- OBF -- Bit 5 -- IBOV -- Bit 4 -- PSPMODE -- Bit 3 -- -- -- Bit 2 RE2 PCFG2 Bit 1 RE1 PCFG1 Bit 0 RE0 PCFG0 Value on: POR, BOR
---- -xxx 0000 -111 ---- -000
Value on all other RESETS
---- -uuu 0000 -111 ---- -000
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
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3.6 Parallel Slave Port FIGURE 3-8:
The Parallel Slave Port is not implemented on the PIC16F73 or PIC16F76. PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In Slave mode, it is asynchronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR. It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits PCFG3:PCFG0 (ADCON1<3:0>) must be set to configure pins RE2:RE0 as digital I/O. There are actually two 8-bit latches. One for data output and one for data input. The user writes 8-bit data to the PORTD data latch and reads data from the port pin latch (note that they have the same address). In this mode, the TRISD register is ignored, since the external device is controlling the direction of data flow. A write to the PSP occurs when both the CS and WR lines are first detected low. When either the CS or WR lines become high (level triggered), the Input Buffer Full (IBF) status flag bit (TRISE<7>) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is complete (Figure 3-9). The interrupt flag bit PSPIF (PIR1<7>) is also set on the same Q4 clock cycle. IBF can only be cleared by reading the PORTD input latch. The Input Buffer Overflow (IBOV) status flag bit (TRISE<5>) is set if a second write to the PSP is attempted when the previous byte has not been read out of the buffer. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full (OBF) status flag bit (TRISE<6>) is cleared immediately (Figure 3-10) indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware. When not in PSP mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previously set, it must be cleared in firmware. An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>).
Data Bus D WR Port Q RDx pin TTL Q RD Port One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) D EN EN
PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)
CK
Read
TTL
RD
Chip Select TTL Write TTL Note: I/O pin has protection diodes to VDD and VSS.
CS
WR
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FIGURE 3-9: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
FIGURE 3-10: PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
TABLE 3-11:
Address 08h 09h 89h 0Ch 8Ch 9Fh
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR
xxxx xxxx
Name PORTD PORTE TRISE PIR1 PIE1 ADCON1
Value on all other RESETS
uuuu uuuu ---- -uuu 0000 -111 0000 0000 0000 0000 ---- -000
Port data latch when written: Port pins when read -- IBF -- OBF -- IBOV RCIF RCIE -- -- PSPMODE TXIF TXIE -- -- -- SSPIF SSPIE -- RE2 RE1 RE0 TMR1IF PORTE Data Direction Bits CCP1IF TMR2IF
---- -xxx 0000 -111 0000 0000 0000 0000 ---- -000
PSPIF(1) ADIF PSPIE --
(1)
ADIE --
CCP1IE TMR2IE TMR1IE PCFG2 PCFG1 PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
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4.0 READING PROGRAM MEMORY
The FLASH Program Memory is readable during normal operation over the entire VDD range. It is indirectly addressed through Special Function Registers (SFR). Up to 14-bit numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that forms an invalid instruction results in a NOP. There are five SFRs used to read the program and memory. These registers are: * * * * * PMCON1 PMDATA PMDATH PMADR PMADRH When interfacing to the program memory block, the PMDATH:PMDATA registers form a two byte word, which holds the 14-bit data for reads. The PMADRH:PMADR registers form a two byte word, which holds the 13-bit address of the FLASH location being accessed. These devices can have up to 8K words of program FLASH, with an address range from 0h to 3FFFh. The unused upper bits in both the PMDATH and PMADRH registers are not implemented and read as "0's".
4.1
PMADR
The address registers can address up to a maximum of 8K words of program FLASH. When selecting a program address value, the MSByte of the address is written to the PMADRH register and the LSByte is written to the PMADR register. The upper MSbits of PMADRH must always be clear.
The program memory allows word reads. Program memory access allows for checksum calculation and reading calibration tables.
4.2
PMCON1 Register
PMCON1 is the control register for memory accesses. The control bit RD initiates read operations. This bit cannot be cleared, only set, in software. It is cleared in hardware at the completion of the read operation.
REGISTER 4-1: PMCON1 REGISTER (ADDRESS 18Ch)
R-1 -- bit 7 bit 7 bit 6-1 bit 0 Reserved: Read as `1' Unimplemented: Read as '0' RD: Read Control bit 1 = Initiates a FLASH read, RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a FLASH read Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-x -- U-0 -- U-0 -- R/S-0 RD bit 0
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4.3 Reading the FLASH Program Memory
A program memory location may be read by writing two bytes of the address to the PMADR and PMADRH registers and then setting control bit RD (PMCON1<0>). Once the read control bit is set, the microcontroller will use the next two instruction cycles to read the data. The data is available in the PMDATA and PMDATH registers after the second NOP instruction. Therefore, it can be read as two bytes in the following instructions. The PMDATA and PMDATH registers will hold this value until another read operation.
EXAMPLE 4-1:
FLASH PROGRAM READ
BSF BCF MOVF MOVWF MOVF MOVWF BSF STATUS, RP1 STATUS, RP0 ADDRH, W PMADRH ADDRL, W PMADR STATUS, RP0 PMCON1, RD ; ; Bank 2 ; ; MSByte of Program Address to read ; ; LSByte of Program Address to read ; Bank 3 ; EEPROM Read
Required Sequence
BSF
NOP NOP
; memory is read in the next two cycles after BSF PMCON1,RD ;
BCF
STATUS, RP0
; Bank 2
MOVF MOVF
PMDATA, W PMDATH, W
; W = LSByte of Program PMDATA ; W = MSByte of Program PMDATA
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4.4 Operation During Code Protect
FLASH program memory has its own code protect mechanism. External Read and Write operations are disabled if this mechanism is enabled. The microcontroller can read and execute instructions out of the internal FLASH program memory, regardless of the state of the code protect configuration bits.
TABLE 4-1:
Address
10Dh 10Fh 10Ch 10Eh 18Ch
REGISTERS ASSOCIATED WITH PROGRAM FLASH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR
xxxx xxxx
-- Address Register High Byte
Name
PMADR PMADRH PMDATA PMDATH PMCON1
Value on all other RESETS
uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1--- ---0
Address Register Low Byte -- --
xxxx xxxx xxxx xxxx xxxx xxxx
Data Register Low Byte -- --(1) -- -- Data Register High Byte -- -- -- -- -- RD
1--- ---0
Legend:
Note 1:
x = unknown, u = unchanged, r = reserved, - = unimplemented read as '0'. Shaded cells are not used during FLASH access. This bit always reads as a `1'.
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5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5.2. The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler is not readable or writable. Section 5.3 details the operation of the prescaler.
Figure 5-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. Additional information on the Timer0 module is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023). Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
5.1
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module Interrupt Service Routine, before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut off during SLEEP.
FIGURE 5-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (= FOSC/4)
0 RA4/T0CKI pin 1 T0SE
M U X
T0CS
PSA PRESCALER
Set Flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
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5.2 Using Timer0 with an External Clock
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. This prescaler is not readable or writable (see Figure 5-1). The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. Note: Writing to TMR0 when the prescaler is assigned to Timer0, will clear the prescaler count but will not change the prescaler assignment.
5.3
Prescaler
There is only one prescaler available, which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. A prescaler assignment for the
REGISTER 5-1: OPTION_REG REGISTER
R/W-1 RBPU bit 7 bit 7 bit 6 bit 5 RBPU INTEDG T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits
Bit Value
000 001 010 011 100 101 110 111
R/W-1 INTEDG
R/W-1 T0CS
R/W-1 T0SE
R/W-1 PSA
R/W-1 PS2
R/W-1 PS1
R/W-1 PS0 bit 0
bit 4
bit 3
bit 2-0
TMR0 Rate
1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
WDT Rate
1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
Legend: R = Readable bit - n = Value at POR reset Note: W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
To avoid an unintended device RESET, the instruction sequence shown in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
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TABLE 5-1:
Address 01h,101h 0Bh,8Bh, 10Bh,18Bh 81h,181h
REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR
xxxx xxxx
Value on all other RESETS
uuuu uuuu 0000 000u 1111 1111
TMR0 INTCON
Timer0 Module's Register GIE PEIE T0IE T0CS INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0
0000 000x 1111 1111
OPTION_REG RBPU INTEDG
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
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6.0 TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>). Timer1 can operate in one of two modes: * As a timer * As a counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Timer1 also has an internal "RESET input". This RESET can be generated by either of the two CCP modules (Section 8.0). Register 6-1 shows the Timer1 Control register. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored and these pins read as `0'. Additional information on timer modules is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023).
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 -- bit 7 bit 7-6 bit 5-4 Unimplemented: Read as `0' T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain) T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0
T1OSCEN T1SYNC TMR1CS TMR1ON
bit 3
bit 2
bit 0
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6.1 Timer1 Operation in Timer Mode 6.2 Timer1 Counter Operation
Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect, since the internal clock is always in sync. Timer1 may operate in Asynchronous or Synchronous mode, depending on the setting of the TMR1CS bit. When Timer1 is being incremented via an external source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment.
FIGURE 6-1:
T1CKI (Default high)
TIMER1 INCREMENTING EDGE
T1CKI (Default low)
Note: Arrows indicate counter increments.
6.3
Timer1 Operation in Synchronized Counter Mode
Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RC1/T1OSI/CCP2, when bit T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter. In this configuration, during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. The prescaler however, will continue to increment.
FIGURE 6-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit TMR1IF on Overflow TMR1H
TMR1 TMR1L
0 1 TMR1ON On/Off T1SYNC
Synchronized Clock Input
T1OSC RC0/T1OSO/T1CKI
(2)
1 T1OSCEN Fosc/4 Enable Internal Oscillator(1) Clock Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS
Synchronize det Q Clock
RC1/T1OSI/CCP2
(2)
Note 1: 2:
When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. For the PIC16F73/76, the Schmitt Trigger is not implemented in External Clock mode.
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6.4 Timer1 Operation in Asynchronous Counter Mode TABLE 6-1:
Osc Type LP
CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR
Freq C1 C2
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 6.4.1). In Asynchronous Counter mode, Timer1 can not be used as a time base for capture or compare operations. 6.4.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will guarantee a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Examples 12-2 and 12-3 in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode.
32 kHz 33 pF 33 pF 100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF These values are for design guidance only. Crystals Tested: 32.768 kHz Epson C-001R32.768K-A 20 PPM 100 kHz Epson C-2 100.00 KC-P 20 PPM 200 kHz STD XTL 200.000 kHz 20 PPM Note 1: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
6.6
Resetting Timer1 using a CCP Trigger Output
If the CCP1 or CCP2 module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1. Note: The special event triggers from the CCP1 and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>).
6.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for use with a 32 kHz crystal. Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.
Timer1 must be configured for either Timer or Synchronized Counter mode, to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for Timer1.
6.7
Resetting of Timer1 Register Pair (TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected.
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.
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TABLE 6-2:
Address
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 GIE PSPIF(1) PSPIE(1) Bit 6 PEIE ADIF ADIE Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on: POR, BOR Value on all other RESETS
Name
0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 0Eh 0Fh 10h PIR1 PIE1 TMR1L
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register T1CON -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
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7.0 TIMER2 MODULE
7.1 Timer2 Prescaler and Postscaler
Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Register 7-1 shows the Timer2 control register. Additional information on timer modules is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023). The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR2 register * a write to the T2CON register * any device RESET (POR, MCLR Reset, WDT Reset or BOR) TMR2 is not cleared when T2CON is written.
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate shift clock.
FIGURE 7-1:
Sets Flag bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2 (1) Output Reset Prescaler 1:1, 1:4, 1:16 2 T2CKPS1: T2CKPS0
TMR2 reg Comparator
FOSC/4
Postscaler 1:1 to 1:16 4 T2OUTPS3: T2OUTPS0
EQ
PR2 reg
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0 -- bit 7 bit 7 bit 6-3 Unimplemented: Read as `0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 TOUTPS1 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 TOUTPS3 TOUTPS2 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 2
bit 1-0
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TABLE 7-1:
Address Name
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7 GIE PSPIF(1) PSPIE(1) Bit 6 PEIE ADIF ADIE Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on: POR, BOR Value on all other RESETS
0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 11h 12h 92h Legend: Note 1: PIR1 PIE1 TMR2 T2CON PR2
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Timer2 Module's Register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000
1111 1111 1111 1111
Timer2 Period Register
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
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8.0 CAPTURE/COMPARE/PWM MODULES
8.2 CCP2 Module
Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: * 16-bit Capture register * 16-bit Compare register * PWM Master/Slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation, with the exception being the operation of the special event trigger. Table 8-1 and Table 8-2 show the resources and interactions of the CCP module(s). In the following sections, the operation of a CCP module is described with respect to CCP1. CCP2 operates the same as CCP1, except where noted. Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Additional information on CCP modules is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023) and in Application Note 594, "Using the CCP Modules" (DS00594).
TABLE 8-1:
CCP MODE - TIMER RESOURCES REQUIRED
Timer Resource Timer1 Timer1 Timer2
8.1
CCP1 Module
CCP Mode Capture Compare PWM
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1.
TABLE 8-2:
INTERACTION OF TWO CCP MODULES
Interaction Same TMR1 time base. The compare should be configured for the special event trigger, which clears TMR1. The compare(s) should be configured for the special event trigger, which clears TMR1. The PWMs will have the same frequency and update rate (TMR2 interrupt). None. None.
CCPx Mode CCPy Mode Capture Capture Compare PWM PWM PWM Capture Compare Compare PWM Capture Compare
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REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1Dh)
U-0 -- bit 7 bit 7-6 bit 5-4 Unimplemented: Read as '0' CCPxX:CCPxY: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 CCPxX R/W-0 CCPxY R/W-0 CCPxM3 R/W-0 CCPxM2 R/W-0 CCPxM1 R/W-0 CCPxM0 bit 0
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8.3 Capture Mode
8.3.2 TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following and is configured by CCPxCON<3:0>: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. 8.3.3 SOFTWARE INTERRUPT
An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value. 8.3.1 CCP PIN CONFIGURATION
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode. 8.3.4 CCP PRESCALER
There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any RESET will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 pin is configured as an output, a write to the port can cause a capture condition.
FIGURE 8-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
EXAMPLE 8-1:
CLRF MOVLW
Set Flag bit CCP1IF (PIR1<2>) Prescaler / 1, 4, 16 RC2/CCP1 Pin and edge detect CCPR1H Capture Enable TMR1H CCP1CON<3:0> Q's TMR1L CCPR1L
CHANGING BETWEEN CAPTURE PRESCALERS
MOVWF
CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; move value and CCP ON CCP1CON ;Load CCP1CON with this ; value
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8.4 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: * Driven high * Driven low * Remains unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. The special event trigger output of CCP2 resets the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP1 and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>).
8.5
PWM Mode (PWM)
FIGURE 8-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch.
Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>). Special Event Trigger Set Flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Q S Output Logic Match RC2/CCP1 R Pin TRISC<2> Output Enable CCP1CON<3:0> Mode Select Comparator TMR1H TMR1L
Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 8.5.3.
FIGURE 8-3:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers CCPR1L
8.4.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch. TIMER1 MODE SELECTION
CCPR1H (Slave)
Comparator
R
Q RC2/CCP1
8.4.2
TMR2
(Note 1) S TRISC<2> Clear Timer, CCP1 pin and latch D.C.
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 8.4.3 SOFTWARE INTERRUPT MODE
Comparator
PR2
When Generate Software Interrupt mode is chosen, the CCP1 pin is not affected. The CCPIF bit is set causing a CCP interrupt (if enabled). 8.4.4 SPECIAL EVENT TRIGGER
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time base.
In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1.
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A PWM output (Figure 8-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). 8.5.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) * Tosc * (TMR2 prescale value)
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
FIGURE 8-4:
TMR2 RESET
PWM OUTPUT
TMR2 RESET Period
CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Maximum PWM resolution (bits) for a given PWM frequency: FOSC log( FPWM Resolution = bits log(2)
8.5.1
PWM PERIOD
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 8.3) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
)
Note:
If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. SET-UP FOR PWM OPERATION
8.5.3
The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
TABLE 8-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
1.22 kHz 16 0xFF 10 4.88 kHz 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 156.3 kHz 1 0x1F 7 208.3 kHz 1 0x17 5.5
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
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TABLE 8-4:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Bit 7
GIE PSPIF(1) -- PSPIE(1) --
Name
Bit 6
PEIE ADIF -- ADIE --
Bit 5
T0IE RCIF -- RCIE --
Bit 4
INTE TXIF -- TXIE --
Bit 3
RBIE SSPIF -- SSPIE --
Bit 2
T0IF CCP1IF -- CCP1IE --
Bit 1
INTF TMR2IF -- TMR2IE --
Bit 0
RBIF
Value on: POR, BOR
Value on all other RESETS
0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 0Dh 8Ch 8Dh 87h 0Eh 0Fh 10h 15h 16h 17h 1Bh 1Ch 1Dh PIR1 PIR2 PIE1 PIE2 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0 TMR1IE 0000 0000 0000 0000 CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
PORTC Data Direction Register Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM register1 (LSB) Capture/Compare/PWM register1 (MSB) -- -- CCP1X CCP1Y CCP1M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM register2 (LSB) Capture/Compare/PWM register2 (MSB) -- -- CCP2X CCP2Y CCP2M3
CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: The PSP is not implemented on the PIC16F73/76; always maintain these bits clear.
TABLE 8-5:
Address
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 GIE PSPIF(1) -- PSPIE(1) -- Bit 6 PEIE ADIF -- ADIE -- Bit 5 T0IE RCIF -- RCIE -- Bit 4 INTE TXIF -- TXIE -- Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 T0IF CCP1IF -- CCP1IE -- Bit 1 INTF TMR2IF -- TMR2IE -- Bit 0 RBIF Value on: POR, BOR Value on all other RESETS
Name
0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 0Dh 8Ch 8Dh PIR1 PIR2 PIE1 PIE2
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0 TMR1IE 0000 0000 0000 0000 CCP2IE ---- ---0 ---- ---0
87h
11h 92h 12h 15h 16h 17h 1Bh 1Ch 1Dh
TRISC
TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON
PORTC Data Direction Register
Timer2 module's register Timer2 module's period register --
1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Capture/Compare/PWM register1 (LSB) Capture/Compare/PWM register1 (MSB) -- -- CCP1X CCP1Y
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Capture/Compare/PWM register2 (LSB) Capture/Compare/PWM register2 (MSB) -- -- CCP2X CCP2Y
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
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9.0
9.1
SYNCHRONOUS SERIAL PORT (SSP) MODULE
SSP Module Overview
9.2
SPI Mode
The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) An overview of I2C operations and additional information on the SSP module can be found in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023). Refer to Application Note AN578, "Use of the SSP Module in the I 2C Multi-Master Environment."
This section contains register definitions and operational characteristics of the SPI module. Additional information on the SPI module can be found in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023A). SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) RC5/SDO * Serial Data In (SDI) RC4/SDI/SDA * Serial Clock (SCK) RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) RA5/SS/AN4 When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: * * * * Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Clock edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only)
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REGISTER 9-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 SMP bit 7 bit 7 SMP: SPI Data Input Sample Phase SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire(R)) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I2 C mode: This bit must be maintained clear bit 6 CKE: SPI Clock Edge Select (Figure 9-2, Figure 9-3, and Figure 9-4) SPI mode: CKP = 0 1 = Data transmitted on rising edge of SCK (Microwire(R) alternate) 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK (Microwire(R) default) 0 = Data transmitted on rising edge of SCK I2 C mode: This bit must be maintained clear bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: STOP bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the START bit is detected last. SSPEN is cleared. 1 = Indicates that a STOP bit has been detected last (this bit is '0' on RESET) 0 = STOP bit was not detected last S: START bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the STOP bit is detected last. SSPEN is cleared. 1 = Indicates that a START bit has been detected last (this bit is '0' on RESET) 0 = START bit was not detected last R/W: Read/Write bit Information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit, or ACK bit. 1 = Read 0 = Write UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0 WCOL bit 7 bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In SPI mode: 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level (Microwire(R) default) 0 = Idle state for clock is a low level (Microwire(R) alternate) In I2 C mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1011 = I2C firmware controlled Master mode (slave idle) 1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
bit 6
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FIGURE 9-1: SSP BLOCK DIAGRAM (SPI MODE)
Internal Data Bus Read SSPBUF reg Write
To enable the serial port, SSP enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is: * SDI must have TRISC<4> set * SDO must have TRISC<5> cleared * SCK (Master mode) must have TRISC<3> cleared * SCK (Slave mode) must have TRISC<3> set * SS must have TRISA<5> set and ADCON must be configured such that RA5 is a digital I/O . Note 1: When the SPI is in Slave mode with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS pin is set to VDD.
SSPSR reg RC4/SDI/SDA RC5/SDO bit0 Shift Clock
SS Control Enable RA5/SS/AN4 Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TRISC<3>
2: If the SPI is used in Slave mode with CKE = '1', then the SS pin control must be enabled.
TMR2 Output 2
Prescaler TCY 4, 16, 64
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FIGURE 9-2:
SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO SDI (SMP = 0) bit7 SDI (SMP = 1) bit7 SSPIF bit0 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SPI MODE TIMING, MASTER MODE
FIGURE 9-3:
SS (optional)
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SCK (CKP = 0) SCK (CKP = 1)
SDO SDI (SMP = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7 SSPIF
bit0
FIGURE 9-4:
SS
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SCK (CKP = 0) SCK (CKP = 1)
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0) bit7 SSPIF bit0
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TABLE 9-1:
Address
REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 GIE PSPIF(1) PSPIE
(1)
Bit 6 PEIE ADIF ADIE
Bit 5 T0IE RCIF RCIE
Bit 4 INTE TXIF TXIE
Bit 3 RBIE SSPIF SSPIE
Bit 2 T0IF
Bit 1 INTF
Bit 0 RBIF
Value on: POR, BOR
Value on all other RESETS
0Bh,8Bh. INTCON 10Bh,18Bh 0Ch 8Ch 87h 13h 14h 85h 94h PIR1 PIE1 TRISC SSPBUF
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
1111 1111 1111 1111 xxxx xxxx uuuu uuuu
PORTC Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register SSPOV SSPEN -- CKE CKP SSPM3 SSPM2 SSPM1 SSPM0
SSPCON WCOL TRISA SSPSTAT -- SMP
0000 0000 0000 0000 --11 1111 --11 1111
PORTA Data Direction Register D/A P S R/W UA BF
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
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9.3 SSP I2 C Operation
The SSP module in I2C mode, fully implements all slave functions, except general call support, and provides interrupts on START and STOP bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The SSP module functions are enabled by setting SSP enable bit SSPEN (SSPCON<5>). The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: * I 2C Slave mode (7-bit address) * I 2C Slave mode (10-bit address) * I 2C Slave mode (7-bit address), with START and STOP bit interrupts enabled to support firmware Master mode * I 2C Slave mode (10-bit address), with START and STOP bit interrupts enabled to support firmware Master mode * I 2C START and STOP bit interrupts enabled to support firmware Master mode, Slave is idle Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. Additional information on SSP I 2C operation can be found in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023A). 9.3.1 SLAVE MODE
FIGURE 9-5:
SSP BLOCK DIAGRAM (I2C MODE)
Internal Data Bus Read SSPBUF reg Shift Clock SSPSR reg Write
RC3/SCK/SCL
RC4/ SDI/ SDA
MSb
LSb Addr Match
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. There are certain conditions that will cause the SSP module not to give this ACK pulse. They include (either or both): a) The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received.
Match Detect
SSPADD reg START and STOP bit Detect Set, RESET S, P bits (SSPSTAT reg)
The SSP module has five registers for I C operation. These are the: * * * * * SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible SSP Address Register (SSPADD)
2
b)
In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 9-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirements of the SSP module, are shown in timing parameter #100 and parameter #101.
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9.3.1.1 Addressing 1. 2. Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1<3>) is set (interrupt is generated if enabled) - on the falling edge of the ninth SCL pulse. Receive first (high) byte of address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of address, if match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated START condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.
3. 4. 5.
6. 7. 8. 9.
In 10-bit address mode, two address bytes need to be received by the slave (Figure 9-7). The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 - 9 for slave-transmitter:
TABLE 9-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
SSPSR SSPBUF Yes No No Generate ACK Pulse Yes No No Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes
Status Bits as Data Transfer is Received BF 0 1 1 0 Note: SSPOV 0 0 1
1 No No Yes Shaded cells show the conditions where the user software did not properly clear the overflow condition.
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9.3.1.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON<6>) is set. This is an error condition due to the user's firmware. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte.
FIGURE 9-6:
I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
SDA
Receiving Address Receiving Data R/W=0 Receiving Data ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL
SSPIF (PIR1<3>)
Cleared in software
Bus Master terminates transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
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9.3.1.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 9-7). An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 9-7:
I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address R/W = 1 A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 ACK
SDA
A7
A6
A5
A4
A3
A2
SCL
S
1 2 Data in sampled
3
4
5
6
7
8
9
1 SCL held low while CPU responds to SSPIF
2
3
4
5
6
7
8
9
P
SSPIF (PIR1<3>) BF (SSPSTAT<0>)
Cleared in software
SSPBUF is written in software CKP (SSPCON<4>)
From SSP Interrupt Service Routine
Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set)
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9.3.2 MASTER MODE 9.3.3 MULTI-MASTER MODE Master mode of operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle and both the S and P bits are clear. In Master mode, the SCL and SDA lines are manipulated by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when transmitting data, a '1' data bit must have the TRISC<4> bit set (input) and a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt will occur if enabled): * START condition * STOP condition * Data transfer byte transmitted/received Master mode of operation can be done with either the Slave mode idle (SSPM3:SSPM0 = 1011), or with the Slave active. When both Master and Slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. In Multi-Master mode, the interrupt generation on the detection of the START and STOP conditions, allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs. In Multi-Master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are: * Address Transfer * Data Transfer When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time.
TABLE 9-3:
Address 0Bh, 8Bh, 10Bh,18Bh 0Ch 8Ch 13h 93h 14h 94h 87h
REGISTERS ASSOCIATED WITH I2C OPERATION
Name Bit 7 GIE PSPIF(1) PSPIE(1) Bit 6 PEIE ADIF ADIE Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR
0000 000x
Value on all other RESETS
0000 000u
INTCON PIR1 PIE1 SSPBUF SSPADD SSPCON SSPSTAT TRISC
SSPIF CCP1IF TMR2IF TMR1IF SSPIE CCP1IE TMR2IE TMR1IE
0000 0000 0000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 1111 1111
0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 1111 1111
Synchronous Serial Port Receive Buffer/Transmit Register Synchronous Serial Port WCOL SMP
(2)
(I2C
mode) Address Register CKP P SSPM3 SSPM2 SSPM1 SSPM0 S R/W UA BF
SSPOV SSPEN CKE
(2)
D/A
PORTC Data Direction register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in I2C mode. Note 1: PSPIF and PSPIE are reserved on the PIC16F73/76; always maintain these bits clear. 2: Maintain these bits clear in I2C mode.
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NOTES:
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10.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)
The USART can be configured in the following modes: * Asynchronous (full duplex) * Synchronous - Master (half duplex) * Synchronous - Slave (half duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 CSRC bit 7 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: bit 4 SREN/CREN overrides TXEN in SYNC mode. SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as '0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of transmit data. Can be parity bit. Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
bit 5
bit 3 bit 2
bit 0
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REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 bit 2 Unimplemented: Read as '0' FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data Can be parity bit (parity to be calculated by firmware) Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 RX9 R/W-0 SREN R/W-0 CREN U-0 -- R-0 FERR R-0 OERR R-x RX9D bit 0
bit 6
bit 5
bit 1
bit 0
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10.1 USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 10-1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode (internal clock). Given the desired baud rate and Fosc, the nearest integer value for the SPBRG register can be calculated using the formula in Table 10-1. From this, the error in baud rate can be determined. It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. 10.1.1 SAMPLING
The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin.
TABLE 10-1:
SYNC 0 1
BAUD RATE FORMULA
BRGH = 0 (Low Speed) (Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) BRGH = 1 (High Speed) Baud Rate= FOSC/(16(X+1)) N/A
X = value in SPBRG (0 to 255)
TABLE 10-2:
Address 98h 18h 99h
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7 CSRC SPEN Bit 6 TX9 RX9 Bit 5 TXEN Bit 4 SYNC Bit 3 -- -- Bit 2 BRGH FERR Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS
0000 -010 0000 -00x 0000 0000
Name TXSTA RCSTA
SREN CREN
TRMT TX9D 0000 -010 OERR RX9D 0000 -00x
0000 0000
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
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TABLE 10-3:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz % ERROR 1.75 0.17 1.73 1.72 8.51 3.34 8.51 FOSC = 4 MHz SPBRG VALUE (DECIMAL) 255 129 31 15 9 8 4 255 0 FOSC = 16 MHz % ERROR 0.17 0.17 0.16 0.16 3.55 6.29 8.51 SPBRG VALUE (DECIMAL) 207 103 25 12 8 6 3 255 0 FOSC = 10 MHz % ERROR 0.17 0.17 1.73 1.72 8.51 6.99 9.58 SPBRG VALUE (DECIMAL) 129 64 15 7 4 4 2 255 0
KBAUD 1.221 2.404 9.766 19.531 31.250 34.722 62.500 1.221 312.500
KBAUD 1.202 2.404 9.615 19.231 27.778 35.714 62.500 0.977 250.000
KBAUD 1.202 2.404 9.766 19.531 31.250 31.250 52.083 0.610 156.250
FOSC = 3.6864 MHz % ERROR 0.33 1.33 1.33 2.90 2.90 2.90 SPBRG VALUE (DECIMAL) 185 46 22 5 2 0 255 0
BAUD RATE (K) KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW 0.300 1.202 2.404 8.929 20.833 31.250 62.500 0.244 62.500
% ERROR 0 0.17 0.17 6.99 8.51 8.51 8.51 -
SPBRG VALUE (DECIMAL) 207 51 25 6 2 1 0 255 0
KBAUD 0.301 1.216 2.432 9.322 18.643 55.930 0.218 55.930
TABLE 10-4:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW BAUD RATE (K) KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW 1.202 2.404 9.615 19.231 27.798 35.714 62.500 0.977 250.000
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz % ERROR 0.16 0.16 0.94 0.55 3.34 FOSC = 4 MHz % ERROR 0.17 0.17 0.16 0.16 3.55 6.29 8.51 SPBRG VALUE (DECIMAL) 207 103 25 12 8 6 3 255 0 SPBRG VALUE (DECIMAL) 129 64 42 36 20 255 0 FOSC = 16 MHz % ERROR 0.16 0.16 2.13 0.79 2.13 SPBRG VALUE (DECIMAL) 103 51 33 29 16 255 0 FOSC = 10 MHz % ERROR 1.71 0.16 1.72 1.36 2.10 1.36 SPBRG VALUE (DECIMAL) 255 64 31 21 18 10 255 0
KBAUD 9.615 19.231 29.070 33.784 59.524 4.883 1250.000
KBAUD 9.615 19.231 29.412 33.333 58.824 3.906 1000.000
KBAUD 2.441 9.615 19.531 28.409 32.895 56.818 2.441 625.000
FOSC = 3.6864 MHz % ERROR 0.25 0.25 1.32 2.90 2.90 4.88 2.90 SPBRG VALUE (DECIMAL) 185 92 22 11 7 6 3 255 0
KBAUD 1.203 2.406 9.727 18.643 27.965 31.960 55.930 0.874 273.722
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10.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-tozero (NRZ) format (one START bit, eight or nine data bits, and one STOP bit). The most common data format is 8-bits. An on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART's transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver USART ASYNCHRONOUS TRANSMITTER (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. TXIF is cleared by loading TXREG. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data and the baud rate generator (BRG) has produced a shift clock (Figure 10-2). The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN. Normally, when transmission is first started, the TSR register is empty. At that point, transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A back-to-back transfer is thus possible (Figure 10-3). Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. As a result, the RC6/TX/CK pin will revert to hi-impedance. In order to select 9-bit transmission, transmit bit TX9 (TXSTA<6>) should be set and the ninth bit should be written to TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register.
10.2.1
The USART transmitter block diagram is shown in Figure 10-1. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE
FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXIE MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN TXREG register 8 *** TSR Register LSb 0 Pin Buffer and Control RC6/TX/CK pin
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Steps to follow when setting up an Asynchronous Transmission: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 10.1) Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. 5. 6. 7. 8. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that GIE and PIE in the INTCON register are set.
2. 3. 4.
FIGURE 10-2: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1
START Bit
Bit 0
Bit 1 Word 1
Bit 7/8
STOP Bit
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 10-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Word 2
START Bit
Bit 0
Bit 1 Word 1
Bit 7/8
STOP Bit START Bit Word 2
Bit 0
Word 1 Transmit Shift Reg.
Word 2 Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 10-5:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- Bit 2 T0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 RBIF TMR1IF RX9D TMR1IE TX9D Value on: POR, BOR
0000 000x 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
Name
Value on all other RESETS
0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h PIR1 RCSTA TXREG PIE1 TXSTA
USART Transmit Register SSPIE CCP1IE TMR2IE -- BRGH TRMT
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
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10.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 10-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate, or at FOSC. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is the receive (serial) shift register (RSR). After sampling the STOP bit, the received data in the RSR is transferred to the RCREG register (if it is empty). If the transfer is complete, flag bit RCIF (PIR1<5>) is set. The actual interrupt can be enabled/ disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only bit which is cleared by the hardware. It is cleared when the RCREG register has been read and is empty. The RCREG is a double buffered register (i.e., it is a two deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, the overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to the RCREG register are inhibited and no further data will be received, therefore, it is essential to clear error bit OERR if it is set. Framing error bit FERR (RCSTA<2>) is set if a STOP bit is detected as clear. Bit FERR and the 9th receive bit are buffered the same way as the receive data. Reading the RCREG will load bits RX9D and FERR with new values, therefore, it is essential for the user to read the RCSTA register before reading RCREG register, in order not to lose the old FERR and RX9D information.
FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK CREN FOSC SPBRG Baud Rate Generator RC7/RX/DT Pin Buffer and Control Data Recovery RX9 /64 or /16 MSb STOP (8) 7 RSR Register *** 1 LSb 0 START OERR FERR
SPEN
RX9D
RCREG Register
FIFO
8 Interrupt RCIF RCIE Data Bus
FIGURE 10-5: ASYNCHRONOUS RECEPTION
RX (pin) Rcv Shift reg Rcv Buffer reg Read Rcv Buffer reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware. START bit bit0 bit1 bit7/8 STOP bit START bit bit0 bit7/8 STOP bit START bit bit7/8 STOP bit
WORD 1 RCREG
WORD 2 RCREG
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Steps to follow when setting up an Asynchronous Reception: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 10.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting bit CREN. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that GIE and PIE in the INTCON register are set.
2. 3. 4. 5.
TABLE 10-6:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 GIE PSPIF(1) SPEN
(1)
Name
Bit 6 PEIE ADIF RX9
Bit 5 T0IE RCIF SREN
Bit 4 INTE TXIF CREN
Bit 3 RBIE SSPIF --
Bit 2 T0IF CCP1IF FERR
Bit 1 INTF TMR2IF OERR
Bit 0 RBIF TMR1IF RX9D
Value on: POR, BOR
0000 000x 0000 0000 0000 -00x 0000 0000
Value on all other RESETS
0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA
RCREG USART Receive Register PIE1 TXSTA PSPIE ADIE TX9 RCIE TXEN TXIE SYNC SSPIE CCP1IE -- BRGH TMR2IE TRMT TMR1IE TX9D
0000 0000 0000 -010 0000 0000
CSRC
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
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FIGURE 10-6: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK CREN FOSC SPBRG /64 or /16 MSb STOP (8) 7 RSR Register *** 1 LSb 0 START OERR FERR
Baud Rate Generator RC7/RX/DT Pin Buffer and Control
Data Recovery
RX9
8 SPEN
RX9D
RCREG Register FIFO
8 Interrupt RCIF RCIE Data Bus
TABLE 10-7:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR
0000 000x 0000 0000 0000 -00x 0000 0000
Name
Value on all other RESETS
0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
CCP1IF TMR2IF TMR1IF FERR OERR RX9D
USART Receive Register CCP1IE TMR2IE TMR1IE BRGH TRMT TX9D
0000 0000 0000 -010 0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
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10.3 USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA<7>). 10.3.1 USART SYNCHRONOUS MASTER TRANSMISSION Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to hiimpedance. If either bit CREN or bit SREN is set during a transmission, the transmission is aborted and the DT pin reverts to a hi-impedance state (for a reception). The CK pin will remain an output if bit CSRC is set (internal clock). The transmitter logic, however, is not reset, although it is disconnected from the pins. In order to reset the transmitter, the user has to clear bit TXEN. If bit SREN is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit SREN will be cleared and the serial port will revert back to transmitting, since bit TXEN is still set. The DT line will immediately switch from hiimpedance receive mode to transmit and start driving. To avoid this, bit TXEN should be cleared. In order to select 9-bit transmission, the TX9 (TXSTA<6>) bit should be set and the ninth bit should be written to bit TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG can result in an immediate transfer of the data to the TSR register (if the TSR is empty). If the TSR was empty and the TXREG was written before writing the "new" TX9D, the "present" value of bit TX9D is loaded. Steps to follow when setting up a Synchronous Master Transmission: 1. 2. 3. 4. 5. 6. 7. 8. Initialize the SPBRG register for the appropriate baud rate (Section 10.1). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PIE in the INTCON register are set.
The USART transmitter block diagram is shown in Figure 10-6. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer register TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one Tcycle), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. TRMT is a read only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock (Figure 10-7). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure 10-8). This is advantageous when slow baud rates are selected, since the BRG is kept in RESET when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally, when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. Back-to-back transfers are possible.
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TABLE 10-8:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 Bit 5 T0IE RCIF Bit 4 INTE TXIF Bit 3 RBIE SSPIF -- Bit 2 T0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 RBIF TMR1IF RX9D Value on: POR, BOR
0000 000x 0000 0000 0000 -00x 0000 0000
Name
Value on all other RESETS
0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h PIR1 RCSTA TXREG PIE1 TXSTA SPBRG
SREN CREN
USART Transmit Register ADIE TX9 RCIE TXEN TXIE SYNC SSPIE -- CCP1IE BRGH TMR2IE TRMT TMR1IE TX9D
0000 0000 0000 -010 0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
FIGURE 10-7: SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg Write Word1 TXIF bit (Interrupt Flag) TRMT TRMT bit '1'
bit 0
bit 1 Word 1
bit 2
bit 7
bit 0
bit 1 Word 2
bit 7
Write Word2
TXEN bit
'1'
Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
FIGURE 10-8: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg bit0 bit1 bit2 bit6 bit7
TXIF bit
TRMT bit
TXEN bit
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10.3.2 USART SYNCHRONOUS MASTER RECEPTION Once synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, CREN takes precedence. After clocking the last bit, the received data in the Receive Shift Register (RSR) is transferred to the RCREG register (if it is empty). When the transfer is complete, interrupt flag bit RCIF (PIR1<5>) is set. The actual interrupt can be enabled/ disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only bit, which is reset by the hardware. In this case, it is reset when the RCREG register has been read and is empty. The RCREG is a double buffered register (i.e., it is a two deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register. On the clocking of the last bit of the third byte, if the RCREG register is still full, then overrun error bit OERR (RCSTA<1>) is set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, so it is essential to clear bit OERR if it is set. The ninth receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG, in order not to lose the old RX9D information. Steps to follow when setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate (Section 10.1). 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that GIE and PIE in the INTCON register are set.
TABLE 10-9:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 T0IF CCP1IF FERR CCP1IE BRGH Bit 1 INTF TMR2IF OERR TMR2IE TRMT Bit 0 RBIF TMR1IF RX9D TMR1IE TX9D Value on: POR, BOR
0000 000x 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
Name
Value on all other RESETS
0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
USART Receive Register
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
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FIGURE 10-9: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit CREN bit RCIF bit (interrupt) Read RXREG '0'
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
'0'
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRG = '0'.
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10.4 USART Synchronous Slave Mode
10.4.2 USART SYNCHRONOUS SLAVE RECEPTION Synchronous Slave mode differs from the Master mode, in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 10.4.1 USART SYNCHRONOUS SLAVE TRANSMIT
The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. Bit SREN is a "don't care" in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h). Steps to follow when setting up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that GIE and PIE in the INTCON register are set.
The operation of the Synchronous Master and Slave modes are identical except in the case of the SLEEP mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from SLEEP and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h).
2. 3. 4. 5.
e)
6.
Steps to follow when setting up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PIE in the INTCON register are set.
7. 8. 9.
2. 3. 4. 5. 6. 7. 8.
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TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address Name Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE -- Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR
0000 000x 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
Value on all other RESETS
0000 000u 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h PIR1 RCSTA TXREG PIE1 TXSTA SPBRG
CCP1IF TMR2IF TMR1IF FERR OERR RX9D
USART Transmit Register CCP1IE TMR2IE TMR1IE BRGH TRMT TX9D
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 T0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE -- Bit 2 T0IF CCP1IF FERR CCP1IE BRGH Bit 1 INTF TMR2IF OERR TMR2IE TRMT Bit 0 RBIF TMR1IF RX9D TMR1IE TX9D Value on: POR, BOR
0000 000x 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
Value on all other RESETS
0000 000u 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
USART Receive Register
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices, always maintain these bits clear.
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NOTES:
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11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The A/D module has three registers. These registers are: * A/D Result Register (ADRES) * A/D Control Register 0 (ADCON0) * A/D Control Register 1 (ADCON1) The ADCON0 register, shown in Register 11-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 11-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference), or as digital I/O. Additional information on using the A/D module can be found in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023) and in Application Note, AN546. The 8-bit analog-to-digital (A/D) converter module has five inputs for the PIC16F73/76 and eight for the PIC16F74/77. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device's positive supply voltage (VDD), or the voltage level on the RA3/AN3/VREF pin. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be derived from the A/D's internal RC oscillator.
REGISTER 11-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 ADCS1 bit 7 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal A/D module RC oscillator) CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) 101 = channel 5, (RE0/AN5)(1) 110 = channel 6, (RE1/AN6)(1) 111 = channel 7, (RE2/AN7)(1) GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1 bit 0 Unimplemented: Read as '0' ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16F74/77 only. Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit 0
bit 5-3
bit 2
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REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0 -- bit 7 bit 7-3 bit 2-0 Unimplemented: Read as '0' PCFG2:PCFG0: A/D Port Configuration Control bits RE0(1) RE1(1) RE2(1) A A D D D D D A A D D D D D A A D D D D D U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0
PCFG2:PCFG0 000 001 010 011 100 101 11x A = Analog input D = Digital I/O
RA0 A A A A A A D
RA1 A A A A A A D
RA2 A A A A D D D
RA5 A A A A D D D
RA3 A VREF A VREF A VREF D
VREF VDD RA3 VDD RA3 VDD RA3 VDD
Note 1: RE0, RE1 and RE2 are implemented on the PIC16F74/77 only. Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog pins / voltage reference / and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set PEIE bit * Set GIE bit 3. 4. 5. Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared (interrupts disabled) OR 6. 7. * Waiting for the A/D interrupt Read A/D result register (ADRES), clear bit ADIF if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts.
2.
FIGURE 11-1: A/D BLOCK DIAGRAM
CHS2:CHS0
111 110 101 100
RE2/AN7(1) RE1/AN6(1) RE0/AN5(1) RA5/AN4
VIN (Input Voltage)
011 010
RA3/AN3/VREF RA2/AN2
A/D Converter
001
RA1/AN1 VDD 000 or 010 or 100 or 11x
001 or 011 or 101 000
RA0/AN0
VREF (Reference Voltage)
PCFG2:PCFG0 Note 1: Not available on PIC16F73/76.
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11.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 11-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), Figure 11-2. The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed), the acquisition must pass before the conversion can be started. To calculate the minimum acquisition time, TACQ, see the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023A). In general, however, given a max of 10k and at a temperature of 100C, TACQ will be no more than 16sec.
FIGURE 11-2: ANALOG INPUT MODEL
VDD VT = 0.6V RIC 1k Sampling Switch SS RSS CHOLD = DAC Capacitance = 51.2 pF VSS Legend CPIN VT = input capacitance = threshold voltage
RS
ANx
VA
CPIN 5 pF
VT = 0.6V
I leakage 500 nA
I leakage = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC)
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch (k)
TABLE 11-1:
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD) Maximum Device Frequency Max. 1.25 MHz 5 MHz 20 MHz (Note 1)
Operation 2TOSC 8TOSC 32TOSC RC(1, 2, 3)
ADCS1:ADCS0 00 01 10 11
Note 1: The RC source has a typical TAD time of 4 s but can vary between 2-6 s. 2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for SLEEP operation. 3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
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11.2 Selecting the A/D Conversion Clock 11.5 A/D Operation During SLEEP
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.0TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: * * * * 2TOSC 8TOSC 32TOSC Internal RC oscillator (2-6 s) The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. Note: For the A/D module to operate in SLEEP, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE bit.
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s.
11.3
Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin that is defined as a digital input, but not as an analog input, may cause the input buffer to consume current that is out of the devices specification.
11.6
Effects of a RESET
A device RESET forces all registers to their RESET state. The A/D module is disabled and any conversion in progress is aborted. All A/D input pins are configured as analog inputs. The ADRES register will contain unknown data after a Power-on Reset.
11.7 11.4
Note:
Use of the CCP Trigger
A/D Conversions
The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. An A/D conversion can be started by the "special event trigger" of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), then the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 counter.
Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, an acquisition is automatically started on the selected channel. The GO/DONE bit can then be set to start the conversion.
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TABLE 11-2:
Address
SUMMARY OF A/D REGISTERS
Bit 7 GIE PSPIF(1)
--
Name
Bit 6 PEIE ADIF
--
Bit 5 T0IE RCIF
--
Bit 4 INTE TXIF
--
Bit 3 RBIE SSPIF
--
Bit 2 T0IF CCP1IF
--
Bit 1 INTF
Bit 0 RBIF
Value on: POR, BOR
Value on all other RESETS
INTCON 0Bh,8Bh, 10Bh,18Bh 0Ch
0Dh
0000 000x 0000 000u
PIR1
PIR2
TMR2IF TMR1IF 0000 0000 0000 0000
-- CCP2IF
---- ---0 ---- ---0
8Ch
8Dh
PIE1
PIE2
PSPIE(1)
--
ADIE
--
RCIE
--
TXIE
--
SSPIE
--
CCP1IE
--
TMR2IE TMR1IE 0000 0000 0000 0000
-- CCP2IE ---- ---0
---- ---0
1Eh 1Fh 9Fh 05h 85h 09h 89h
ADRES ADCON0 ADCON1 PORTA TRISA PORTE
(2)
A/D Result Register ADCS1 -- -- -- -- IBF ADCS0 CHS2 -- -- -- -- OBF -- RA5 -- CHS1 -- RA4 -- CHS0 -- RA3 -- -- GO/DONE PCFG2 RA2 -- PCFG1 RA1 ADON
xxxx xxxx uuuu uuuu 0000 00-0 0000 00-0
PCFG0 ---- -000 ---- -000 RA0
--0x 0000 --0u 0000 --11 1111 --11 1111
PORTA Data Direction Register RE2 RE1 RE0
---- -xxx ---- -uuu 0000 -111 0000 -111
TRISE(2)
IBOV PSPMODE
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear. 2: These registers are reserved on the PIC16F73/76.
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12.0 SPECIAL FEATURES OF THE CPU
These devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * Oscillator Selection * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code Protection * ID Locations * In-Circuit Serial Programming These devices have a Watchdog Timer, which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. Additional information on special features is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
12.1
Configuration Bits
The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space, which can be accessed only during programming.
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REGISTER 12-1: CONFIGURATION WORD
--
bit13 bit 13-7: Unimplemented: Read as `1' bit 6: BODEN: Brown-out Reset Enable bit(1) 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as `1' CP0: Flash Program Memory Code Protection bit 1 = Code protection off 0 = All memory locations code protected PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
--
--
--
--
--
--
BODEN
--
CP0
PWRTE WDTE F0SC1 F0SC0 bit0
Register: CONFIG Address 2007h Erased Value: 3FFFh
bit 5: bit 4
bit 3:
bit 2:
bit 1-0:
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled.
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12.2
12.2.1
Oscillator Configurations
OSCILLATOR TYPES
FIGURE 12-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
The PIC16F7X can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR/CERAMIC RESONATORS
Clock from ext. system Open
OSC1 PIC16F7X OSC2
12.2.2
TABLE 12-1:
CERAMIC RESONATORS
Ranges Tested:
In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 12-1). The PIC16F7X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 12-2). See Table 15-1 for valid external clock frequencies.
Mode XT
Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz
OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
HS
These values are for design guidance only. See notes at bottom of page. Resonators Used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX 0.3% 0.5% 0.5% 0.5% 0.5%
FIGURE 12-1: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
C1(1) OSC1 To internal logic SLEEP PIC16F7X
All resonators used did not have built-in capacitors.
XTAL OSC2 RS(2) C2(1) Note 1:
RF(3)
See Table 12-1 and Table 12-2 for recommended values of C1 and C2.
2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen.
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TABLE 12-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF 12.2.3 RC OSCILLATOR For timing insensitive applications, the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 12-3 shows how the R/C combination is connected to the PIC16F7X.
Osc Type LP XT
Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz
HS
4 MHz 8 MHz 20 MHz
These values are for design guidance only. See notes at bottom of page. Crystals Used 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM
FIGURE 12-3: RC OSCILLATOR MODE
VDD REXT OSC1 CEXT VSS FOSC/4 Recommended values: OSC2/CLKOUT 3 k REXT 100 k CEXT > 20pF Internal Clock PIC16F7X
Note 1: Higher capacitance increases the stability of oscillator, but also increases the startup time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. 4: When migrating from other PICmicro devices, oscillator performance should be verified.
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12.3 RESET
The PIC16F7X differentiates between various kinds of RESET: * * * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR) SLEEP, and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different RESET situations, as indicated in Table 12-4. These bits are used in software to determine the nature of the RESET. See Table 12-6 for a full description of RESET states of all registers. A simplified block diagram of the on-chip RESET circuit is shown in Figure 12-4. These devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low.
Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a "RESET state" on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR Reset during
FIGURE 12-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External RESET MCLR WDT Module VDD rise detect VDD Brown-out Reset OST/PWRT OST 10-bit Ripple counter OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter R Q Chip_Reset Power-on Reset S WDT SLEEP
Time-out Reset
BODEN
Enable PWRT Enable OST Note 1:
This is a separate oscillator from the RC oscillator of the CLKIN pin.
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12.4 Power-on Reset (POR) 12.8 Time-out Sequence
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Poweron Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions. For additional information, refer to Application Note, AN007, "Power-up Trouble Shooting", (DS00007). On power-up, the time-out sequence is as follows: The PWRT delay starts (if enabled) when a POR Reset occurs. Then OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, HS). When the OST ends, the device comes out of RESET. If MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16F7X device operating in parallel. Table 12-5 shows the RESET conditions for the STATUS, PCON and PC registers, while Table 12-6 shows the RESET conditions for all the registers.
12.9
Power Control/Status Register (PCON)
12.5
Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/ disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature and process variation. See DC parameters for details (TPWRT, parameter #33).
The Power Control/Status Register, PCON, has up to two bits depending upon the device. Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if bit BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable and therefore, not valid at any time. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.
12.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024 oscillator cycles (from OSC1 input) delay after the PWRT delay is over (if enabled). This helps to ensure that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.
12.7
Brown-out Reset (BOR)
The configuration bit, BODEN, can enable or disable the Brown-out Reset circuit. If VDD falls below VBOR (parameter D005, about 4V) for longer than TBOR (parameter #35, about 100S), the brown-out situation will reset the device. If VDD falls below VBOR for less than TBOR, a RESET may not occur. Once the brown-out occurs, the device will remain in Brown-out Reset until VDD rises above VBOR. The Power-up Timer then keeps the device in RESET for TPWRT (parameter #33, about 72mS). If VDD should fall below VBOR during TPWRT, the Brown-out Reset process will restart when VDD rises above VBOR, with the Power-up Timer Reset. The Power-up Timer is always enabled when the Brown-out Reset circuit is enabled, regardless of the state of the PWRT configuration bit.
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TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 XT, HS, LP RC 72 ms + 1024TOSC 72 ms PWRTE = 1 1024TOSC -- 72 ms + 1024TOSC 72 ms Brown-out Wake-up from SLEEP 1024TOSC -- Oscillator Configuration
TABLE 12-4:
POR 0 0 0 1 1 1 1 1 BOR x x x 0 1 1 1 1
STATUS BITS AND THEIR SIGNIFICANCE
TO 1 0 x 1 0 0 u 1 PD 1 x 0 1 1 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 12-5:
RESET CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1
(1)
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu
PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
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TABLE 12-6:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Devices
Power-on Reset, MCLR Reset, Wake-up via WDT or Brown-out Reset WDT Reset Interrupt W 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu INDF 73 74 76 77 N/A N/A N/A TMR0 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PCL 73 74 76 77 0000h 0000h PC + 1(2) (3) STATUS 73 74 76 77 0001 1xxx 000q quuu uuuq quuu(3) FSR 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTA 73 74 76 77 --0x 0000 --0u 0000 --uu uuuu PORTB 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTD 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTE 73 74 76 77 ---- -xxx ---- -uuu ---- -uuu PCLATH 73 74 76 77 ---0 0000 ---0 0000 ---u uuuu INTCON 73 74 76 77 0000 000x 0000 000u uuuu uuuu(1) PIR1 73 74 76 77 r000 0000 r000 0000 ruuu uuuu(1) 73 74 76 77 0000 0000 0000 0000 uuuu uuuu(1) PIR2 73 74 76 77 ---- ---0 ---- ---0 ---- ---u(1) TMR1L 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 73 74 76 77 --00 0000 --uu uuuu --uu uuuu TMR2 73 74 76 77 0000 0000 0000 0000 uuuu uuuu T2CON 73 74 76 77 -000 0000 -000 0000 -uuu uuuu SSPBUF 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 73 74 76 77 0000 0000 0000 0000 uuuu uuuu CCPR1L 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 73 74 76 77 --00 0000 --00 0000 --uu uuuu RCSTA 73 74 76 77 0000 -00x 0000 -00x uuuu -uuu TXREG 73 74 76 77 0000 0000 0000 0000 uuuu uuuu RCREG 73 74 76 77 0000 0000 0000 0000 uuuu uuuu CCPR2L 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 73 74 76 77 0000 0000 0000 0000 uuuu uuuu ADRES 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 73 74 76 77 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 73 74 76 77 1111 1111 1111 1111 uuuu uuuu TRISA 73 74 76 77 --11 1111 --11 1111 --uu uuuu TRISB 73 74 76 77 1111 1111 1111 1111 uuuu uuuu TRISC 73 74 76 77 1111 1111 1111 1111 uuuu uuuu TRISD 73 74 76 77 1111 1111 1111 1111 uuuu uuuu TRISE 73 74 76 77 0000 -111 0000 -111 uuuu -uuu PIE1 73 74 76 77 r000 0000 r000 0000 ruuu uuuu 73 74 76 77 0000 0000 0000 0000 uuuu uuuu PIE2 73 74 76 77 ---- ---0 ---- ---0 ---- ---u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved maintain clear. Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 12-5 for RESET value for specific condition.
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TABLE 12-6:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Devices
Power-on Reset, MCLR Reset, Wake-up via WDT or Brown-out Reset WDT Reset Interrupt PCON 73 74 76 77 ---- --qq ---- --uu ---- --uu PR2 73 74 76 77 1111 1111 1111 1111 1111 1111 SSPSTAT 73 74 76 77 --00 0000 --00 0000 --uu uuuu SSPADD 73 74 76 77 0000 0000 0000 0000 uuuu uuuu TXSTA 73 74 76 77 0000 -010 0000 -010 uuuu -uuu SPBRG 73 74 76 77 0000 0000 0000 0000 uuuu uuuu ADCON1 73 74 76 77 ---- -000 ---- -000 ---- -uuu PMDATA 73 74 76 77 0--- 0000 0--- 0000 u--- uuuu PMADR 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PMDATH 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PMADRH 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PMCON1 73 74 76 77 1--- ---0 1--- ---0 1--- ---u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved maintain clear. Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 12-5 for RESET value for specific condition.
FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
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FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-8: SLOW RISE TIME (MCLR TIED TO VDD)
5V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 0V 1V
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PIC16F7X
12.10 Interrupts
The PIC16F7X family has up to 12 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the Special Function Registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in Special Function Registers, PIE1 and PIE2, and the peripheral interrupt enable bit is contained in Special Function Register INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts, or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on RESET. The "return from interrupt" instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts.
FIGURE 12-9: INTERRUPT LOGIC
PSPIF PSPIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE T0IF T0IE INTF INTE RBIF RBIE PEIE GIE Wake-up (If in SLEEP mode)
Interrupt to CPU
The following table shows which devices have which interrupts.
Device PIC16F76/73 PIC16F77/74 T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
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12.10.1 INT INTERRUPT External interrupt on the RB0/INT pin is edge triggered, either rising, if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wakeup. See Section 12.13 for details on SLEEP mode. 12.10.2 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 5.0) 12.10.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 3.2)
12.11
Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (i.e., W register and STATUS register). This will have to be implemented in software. For the PIC16F73/74 devices, the register W_TEMP must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., If W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1.). The registers, PCLATH_TEMP and STATUS_TEMP, are only defined in bank 0. Since the upper 16 bytes of each bank are common in the PIC16F76/77 devices, temporary holding registers W_TEMP, STATUS_TEMP and PCLATH_TEMP should be placed in here. These 16 locations don't require banking and therefore, make it easier for context save and restore. The same code shown in Example 12-1 can be used.
EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF SWAPF CLRF MOVWF MOVF MOVWF CLRF : :(ISR) : MOVF MOVWF SWAPF MOVWF SWAPF SWAPF W_TEMP STATUS,W STATUS STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH ;Copy ;Swap ;bank ;Save ;Only ;Save ;Page W to TEMP register status to be saved into W 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register required if using pages 1, 2 and/or 3 PCLATH into W zero, regardless of current page
;Insert user code here PCLATH_TEMP, W PCLATH STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W ;Restore PCLATH ;Move W into PCLATH ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
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12.12 Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing configuration bit WDTE (Section 12.1). WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition.
. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.
FIGURE 12-10: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 5-1)
0 WDT Timer 1 M U X Postscaler 8 8 - to - 1 MUX WDT Enable Bit PSA
To TMR0 (Figure 5-1)
PS2:PS0
0 MUX
1 PSA
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
WDT Time-out
TABLE 12-7:
Address 2007h 81h,181h
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7 (1) RBPU Bit 6 BODEN(1) INTEDG Bit 5 -- T0CS Bit 4 CP0 T0SE Bit 3 PWRTE(1) PSA Bit 2 WDTE PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0
Name Config. bits OPTION_REG
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of these bits.
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12.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and disable external clocks. Pull all I/O pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should also be considered. The MCLR pin must be at a logic high level (VIHMC). 12.13.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from INT pin, RB port change or a Peripheral Interrupt. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 12.13.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from SLEEP. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
External MCLR Reset will cause a device RESET. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred and caused wake-up. The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. 4. 5. 6. 7. 8. PSP read or write (PIC16F74/77 only). TMR1 interrupt. Timer1 must be operating as an asynchronous counter. CCP Capture mode interrupt. Special event trigger (Timer1 in Asynchronous mode using an external clock). SSP (START/STOP) bit detect interrupt. SSP transmit or receive in Slave mode (SPI/I2C). USART RX or TX (Synchronous Slave mode). A/D conversion (when A/D clock source is RC).
Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present.
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FIGURE 12-11: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: 2: 3: 4:
XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
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12.14 Program Verification/Code Protection 12.16 In-Circuit Serial Programming
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. PIC16F7X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For complete details of serial programming, please refer to the In-Circuit Serial Programming (ICSPTM) Guide, (DS30277).
12.15
ID Locations
Four memory locations (2000h - 2003h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID location are used.
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13.0 INSTRUCTION SET SUMMARY
Each PIC16F7X instruction is a 14-bit word divided into an OPCODE, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The PIC16F7X instruction set summary in Table 13-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 13-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the address of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 13-2 lists the instructions recognized by the MPASM assembler. Figure 13-1 shows the general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16F7X products, do not use the OPTION and TRIS instructions.
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
TABLE 13-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
FIGURE 13-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value
CALL and GOTO instructions only
0
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 Program Counter Time-out bit Power-down bit
0 f (FILE #)
d
PC TO PD
8
7 k (literal)
0
The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations
13
11 OPCODE
10 k (literal)
0
k = 11-bit immediate value
A description of each instruction is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
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TABLE 13-2:
Mnemonic, Operands
PIC16F7X INSTRUCTION SET
Description Cycles 14-Bit Opcode MSb BYTE-ORIENTED FILE REGISTER OPERATIONS Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
LSb
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
Status Affected
Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, b f, b f, b f, b k k k k k k k k k
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2 1,2 1,2 3 3
BIT-ORIENTED FILE REGISTER OPERATIONS
01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff
LITERAL AND CONTROL OPERATIONS
11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023).
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13.1
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add Literal and W [label] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register. Operation: Status Affected: Description: k ANDWF Syntax: Operands: AND W with f [label] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. f,d
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [label] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. f,d
BCF Syntax: Operands: Operation: Status Affected: Description:
Bit Clear f [label] BCF 0 f 127 0b7 0 (f) None Bit 'b' in register 'f' is cleared. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND Literal with W [label] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register. k
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [label] BSF 0 f 127 0b7 1 (f) None Bit 'b' in register 'f' is set. f,b
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [label] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit 'b' in register 'f' is '0', the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead making this a 2TCY instruction. Status Affected: Description: CLRF Syntax: Operands: Operation: Clear f [label] CLRF 0 f 127 00h (f) 1Z Z The contents of register 'f' are cleared and the Z bit is set. f
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test, Skip if Clear [label] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit 'b' in register 'f' is '1', the next instruction is executed. If bit 'b', in register 'f', is '0', the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC) + 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction.
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: Description:
Status Affected: Description:
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COMF Syntax: Operands: Operation: Status Affected: Description: Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. Status Affected: Description: f,d GOTO Syntax: Operands: Operation: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction.
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [label] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
DECFSZ Syntax: Operands: Operation: Status Affected: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register 'f' are decremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 1, the next instruction is executed. If the result is 0, then a NOP is executed instead making it a 2TCY instruction.
INCFSZ Syntax: Operands: Operation: Status Affected: Description:
Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead making it a 2TCY instruction.
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IORLW Syntax: Operands: Operation: Status Affected: Description: Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight bit literal 'k'. The result is placed in the W register. MOVLW Syntax: Operands: Operation: Status Affected: Description: Move Literal to W [ label ] k (W) None The eight bit literal 'k' is loaded into W register. The don't cares will assemble as 0's. MOVLW k 0 k 255
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
MOVWF Syntax: Operands: Operation: Status Affected: Description:
Move W to f [ label ] (W) (f) None Move data from W register to register 'f'. MOVWF f 0 f 127
MOVF Syntax: Operands: Operation: Status Affected: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (destination) Z The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.
NOP Syntax: Operands: Operation: Status Affected: Description:
No Operation [ label ] None No operation None No operation. NOP
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RETFIE Syntax: Operands: Operation: Status Affected: Return from Interrupt [ label ] None TOS PC, 1 GIE None RETFIE RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] RLF f,d 0 f 127 d [0,1] See description below C The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'.
C Register f
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
C Register f
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction. RETURN
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. SLEEP
Status Affected: Description:
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 117
PIC16F7X
SUBLW Syntax: Operands: Operation: Description: Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register. XORLW Syntax: Operands: Operation: Status Affected: Description: Exclusive OR Literal with W [label] XORLW k
0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register.
Status Affected: C, DC, Z
SUBWF Syntax: Operands: Operation: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
XORWF Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f [label] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
Status Affected: C, DC, Z
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W register. If 'd' is 1, the result is placed in register 'f'.
DS30325A-page 118
Advance Information
2000 Microchip Technology Inc.
PIC16F7X
14.0 DEVELOPMENT SUPPORT
MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file - object code The ability to use MPLAB with Microchip's simulator, MPLAB-SIM, allows a consistent platform and the ability to easily switch from the cost-effective simulator to the full featured emulator with minimal retraining. The microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASM Assembler - MPLAB-C17 and MPLAB-C18 C Compilers - MPLINK/MPLIB Linker/Librarian * Simulators - MPLAB-SIM Software Simulator * Emulators - MPLAB-ICE Real-Time In-Circuit Emulator - ICEPICTM * In-Circuit Debugger - MPLAB-ICD for PIC16F87X * Device Programmers - PRO MATE II Universal Programmer - PICSTART Plus Entry-Level Prototype Programmer * Low-Cost Demonstration Boards - PICDEM-1 - PICDEM-2 - PICDEM-3 - PICDEM-17 - KEELOQ PICmicro(R)
14.2
MPASM Assembler
MPASM is a full featured universal macro assembler for all PICmicro MCU's. It can produce absolute code directly in the form of HEX files for device programmers, or it can generate relocatable objects for MPLINK. MPASM has a command line interface and a Windows shell and can be used as a standalone application on a Windows 3.x or greater system. MPASM generates relocatable object files, Intel standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file which contains source lines and generated machine code, and a COD file for MPLAB debugging. MPASM features include: * MPASM and MPLINK are integrated into MPLAB projects. * MPASM allows user defined macros to be created for streamlined assembly. * MPASM allows conditional assembly for multi purpose source files. * MPASM directives allow complete control over the assembly process.
14.1
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a Windows-based application which contains: * Multiple functionality - editor - simulator - programmer (sold separately) - emulator (sold separately) * A full featured editor * A project manager * Customizable tool bar and key mapping * A status bar * On-line help
14.3
MPLAB-C17 and MPLAB-C18 C Compilers
The MPLAB-C17 and MPLAB-C18 Code Development Systems are complete ANSI `C' compilers and integrated development environments for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 119
PIC16F7X
14.4 MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and MPLAB-C17 and MPLAB-C18. It can link relocatable objects from assembly or C source files along with precompiled libraries using directives from a linker script. MPLIB is a librarian for pre-compiled code to be used with MPLINK. When a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. MPLIB manages the creation and modification of library files. MPLINK features include: * MPLINK works with MPASM and MPLAB-C17 and MPLAB-C18. * MPLINK allows all memory areas to be defined as sections to provide link-time flexibility. MPLIB features include: * MPLIB makes linking easier because single libraries can be included instead of many smaller files. * MPLIB helps keep code maintainable by grouping related modules together. * MPLIB commands allow libraries to be created and modules to be added, listed, replaced, deleted, or extracted. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE allows expansion to support new PICmicro microcontrollers. The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. MPLAB-ICE 2000 is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems use the same processor modules and will operate across the full operating speed range of the PICmicro MCU.
14.7
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X, and PIC16CXXX families of 8-bit one-timeprogrammable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules or daughter boards. The emulator is capable of emulating without target application circuitry being present.
14.5
MPLAB-SIM Software Simulator
14.8
MPLAB-ICD In-Circuit Debugger
The MPLAB-SIM Software Simulator allows code development in a PC host environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file or user-defined key press to any of the pins. The execution can be performed in single step, execute until break, or trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPLAB-C18 and MPASM. The Software Simulator offers the flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
14.6
MPLAB-ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
Microchip's In-Circuit Debugger, MPLAB-ICD, is a powerful, low-cost run-time development tool. This tool is based on the flash PIC16F877 and can be used to develop for this and other PICmicro microcontrollers from the PIC16CXXX family. MPLAB-ICD utilizes the In-Circuit Debugging capability built into the PIC16F87X. This feature, along with Microchip's In-Circuit Serial Programming protocol, offers cost-effective in-circuit flash programming and debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in real-time. The MPLAB-ICD is also a programmer for the flash PIC16F87X family.
The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of MPLAB-ICE is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment.
DS30325A-page 120
Advance Information
2000 Microchip Technology Inc.
PIC16F7X
14.9 PRO MATE II Universal Programmer 14.12
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode the PRO MATE II can read, verify or program PICmicro devices. It can also set code-protect bits in this mode.
PICDEM-2 Low-Cost PIC16CXX Demonstration Board
14.10
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus supports all PICmicro devices with up to 40 pins. Larger pin count devices such as the PIC16C92X, and PIC17C76X may be supported with an adapter socket. PICSTART Plus is CE compliant.
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
14.13
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
14.11
PICDEM-1 Low-Cost PICmicro Demonstration Board
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 121
PIC16F7X
14.14 PICDEM-17
The PICDEM-17 is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756, PIC17C762, and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included, and the user may erase it and program it with the other sample programs using the PRO MATE II or PICSTART Plus device programmers and easily debug and test the sample code. In addition, PICDEM-17 supports down-loading of programs to and executing out of external FLASH memory on board. The PICDEM-17 is also usable with the MPLAB-ICE or PICMASTER emulator, and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware.
14.15
KEELOQ Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
DS30325A-page 122
Advance Information
2000 Microchip Technology Inc.
24CXX/ 25CXX/ 93CXX
TABLE 14-1:
PIC14000
HCSXXX
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
PIC16F62X
PIC16C7XX
PIC16F8XX
PIC16C9XX
PIC17C7XX
PIC12CXXX
PIC16CXXX
Programmers Debugger Emulators Software Tools
Demo Boards and Eval Kits
2000 Microchip Technology Inc.
PIC18CXX2
(R) MPLAB Integrated Development Environment (R) MPLAB C17 Compiler (R) MPLAB C18 Compiler
aaa
MPASM/MPLINK (R) MPLAB -ICE
aa
**
ICEPIC Low-Cost In-Circuit Emulator
(R) MPLAB -ICD In-Circuit Debugger
*
*
PICSTARTPlus Low-Cost Universal Dev. Kit
**
PRO MATE II Universal Programmer
**
PICDEM-1
DEVELOPMENT TOOLS FROM MICROCHIP
aa
PICDEM-2
Advance Information
a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
PICDEM-3
PICDEM-14A
PICDEM-17
KEELOQ(R) Evaluation Kit
aa
KEELOQ Transponder Kit
microIDTM Programmer's Kit
125 kHz microID Developer's Kit
aa a
125 kHz Anticollision microID Developer's Kit
13.56 MHz Anticollision microID Developer's Kit
MCP2510 CAN Developer's Kit
MCRFXXX
PIC16F7X
DS30325A-page 123
(R) * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB -ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77 ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices.
MCP2510
a a aa a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa a a
a
a
a
a
a
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a
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PIC16F7X
NOTES:
DS30325A-page 124
Advance Information
2000 Microchip Technology Inc.
PIC16F7X
15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Ambient temperature under bias................................................................................................................ .-55 to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V Voltage on MCLR with respect to VSS (Note 2)...............................................................................................0 to +13.5V Voltage on RA4 with respect to Vss ...................................................................................................................0 to +12V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3) ...................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ..............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3) ..................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3).............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling this pin directly to VSS. 3: PORTD and PORTE are not implemented on the PIC16F73/76 devices. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 125
PIC16F7X
FIGURE 15-1: PIC16F7X VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V
Voltage
4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V
16 MHz
20 MHz
Frequency
FIGURE 15-2: PIC16LF7X VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V
Voltage
4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V
4 MHz
10 MHz
Frequency
FMAX = (12 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application. Note 2: FMAX has a maximum frequency of 10MHz.
DS30325A-page 126
Advance Information
2000 Microchip Technology Inc.
PIC16F7X
15.1 DC Characteristics
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Supply Voltage PIC16LF7X D001 D001A D002* D003 VDR VPOR PIC16F7X RAM Data Retention Voltage (Note 1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Supply Current (Note 2, 5) PIC16LF7X D010A D010 D013 D015* DIBOR Brown-out Reset Current (Note 6) PIC16F7X 0.6 20 1.6 7 85 2.0 35 4 15 200 mA A mA mA A XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) HS osc configuration FOSC = 20 MHz, VDD = 5.5V BOR enabled VDD = 5.0V 2.0 4.0 VBOR* 1.5 VSS 5.5 5.5 5.5 V V V V V See section on Power-on Reset for details All osc configurations (DC - 10 MHz) All configurations BOR enabled (Note 7) Min Typ Max Units Conditions PIC16LF73/74/76/77 (Industrial) PIC16F73/74/76/77 (Industrial) Param No. D001 Sym VDD
D004*
SVDD
0.05
-
-
V/ms See section on Power-on Reset for details
D005 D010
VBOR IDD
3.65
4.0
4.35
V
BODEN bit in configuration word enabled
Legend: * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 127
PIC16F7X
PIC16LF73/74/76/77 (Industrial) PIC16F73/74/76/77 (Industrial) Param No. D020 D021 D020 D021 D023* PIC16F7X DIBOR Brown-out Reset Current (Note 6) Sym IPD Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min Typ Max Units Conditions
Power-down Current (Note 3, 5) PIC16LF7X 7.5 0.9 10.5 1.5 85 30 5 42 19 200 A A A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +85C BOR enabled VDD = 5.0V
Legend: * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30325A-page 128
Advance Information
2000 Microchip Technology Inc.
PIC16F7X
15.2 DC Characteristics: PIC16F73/74/76/77 (Industrial) PIC16LF73/74/76/77 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Min Typ Max Units Conditions
DC CHARACTERISTICS Param No. Sym VIL D030 D030A D031 D032 D033 Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT and LP mode) OSC1 (in HS mode) Ports RC3 and RC4 with Schmitt Trigger buffer Input High Voltage I/O ports with TTL buffer
VSS VSS VSS VSS VSS VSS VSS
-
0.15VDD 0.8V 0.2VDD 0.2VDD 0.3V 0.3VDD 0.3VDD
V V V V V V V
For entire VDD range 4.5V VDD 5.5V
(Note 1) (Note 1) For entire VDD range
D034 VIH D040 D040A D041 D042 D042A D043 D044 D070 D060 D061 D063
with Schmitt Trigger buffer
2.0 0.25VDD + 0.8V 0.8VDD
VDD VDD VDD VDD VDD VDD VDD VDD 400 1 5 5
V V V V V V V
4.5V VDD 5.5V For entire VDD range For entire VDD range (Note 1) (Note 1)
0.8VDD MCLR OSC1 (in XT and LP mode) 1.6V OSC1 (in HS mode) 0.7VDD OSC1 (in RC mode) 0.9VDD Ports RC3 and RC4 with Schmitt Trigger buffer 0.7VDD IPURB PORTB Weak Pull-up Current 50 250 IIL Input Leakage Current (Notes 2, 3) I/O ports MCLR, RA4/T0CKI OSC1 VOL Output Low Voltage I/O ports OSC2/CLKOUT (RC osc config) VOH Output High Voltage I/O ports (Note 3) -
V For entire VDD range A VDD = 5V, VPIN = VSS A Vss VPIN VDD, Pin at hi-impedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration V V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C RA4 pin
D080 D083
-
-
0.6 0.6
D090 D092
VDD - 0.7
-
-
V V
OSC2/CLKOUT (RC osc config) VDD - 0.7
D150* VOD Open-Drain High Voltage 12 V Legend: * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 129
PIC16F7X
DC CHARACTERISTICS Param No. D100 D101 D102 Sym Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Min Typ Max Units Conditions
Capacitive Loading Specs on Output Pins COSC2 OSC2 pin CIO All I/O pins and OSC2 (in RC mode) CB SCL, SDA in I2C mode -
15 50 400
pF pF pF
In XT, HS and LP modes when external clock is used to drive OSC1
Program FLASH Memory D130 EP Endurance 100 E/W 25C at 5V D131 VPR VDD for read 2.0 5.5 V Legend: * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
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15.3 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free T Time 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only)
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z High Low
Period Rise Valid Hi-impedance High Low
TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition
SU STO
Setup STOP condition
FIGURE 15-3: LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16F73/76 devices.
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PIC16F7X
FIGURE 15-4: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 CLKOUT 3 3 4 4
TABLE 15-1:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym Characteristic Min DC DC DC DC 0.1 4 5 1000 50 5 250 250 50 5 200 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- TCY Max 1 20 32 4 4 20 200 -- -- -- -- 10,000 250 -- DC Units Conditions MHz MHz kHz MHz MHz MHz kHz ns ns ms ns ns ns ms ns XT osc mode HS osc mode LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode XT osc mode HS osc mode LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode TCY = 4/FOSC
FOSC External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1)
1
TOSC External CLKIN Period (Note 1) Oscillator Period (Note 1)
2 3
500 -- -- ns XT oscillator 2.5 -- -- ms LP oscillator 15 -- -- ns HS oscillator 4 TosR, External Clock in (OSC1) Rise -- -- 25 ns XT oscillator TosF or Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator Legend: Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
Instruction Cycle Time (Note 1) TosL, External Clock in (OSC1) High TosH or Low Time
TCY
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FIGURE 15-5: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 15 new value 19 18 12 16 11 Q1 Q2 Q3
20, 21 Note: Refer to Figure 15-3 for load conditions.
TABLE 15-2:
Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18* Sym
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Standard (F) Port input invalid (I/O in Extended (LF) hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time Standard (F) Extended (LF) Standard (F) Extended (LF) Min -- -- -- -- -- TOSC + 200 0 -- 100 200 0 -- -- -- -- Tcy Tcy Typ 75 75 35 35 -- -- -- 100 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5TCY + 20 -- -- 255 -- -- -- 40 145 40 145 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckL TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI
TosH2ckH OSC1 to CLKOUT
19* 20* 21* 22* 23*
TioV2osH TioR TioF Tinp Trbp
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
Legend: *
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PIC16F7X
FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer Reset 34 I/O Pins 32 30
31 34
Note: Refer to Figure 15-3 for load conditions.
FIGURE 15-7: BROWN-OUT RESET TIMING
VDD
VBOR 35
TABLE 15-3:
Parameter No. 30 31* 32 33* 34 35
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Sym Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Min 2 7 -- 28 -- 100 Typ -- 18 1024 TOSC 72 -- -- Max -- 33 -- 132 2.1 -- Units s ms -- ms s s VDD VBOR (D005) Conditions VDD = 5V, -40C to +85C VDD = 5V, -40C to +85C TOSC = OSC1 period VDD = 5V, -40C to +85C
TmcL Twdt Tost Tpwrt TIOZ TBOR
Legend: * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC16F7X
FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
40
41
42
RC0/T1OSO/T1CKI
45
46
47
48
TMR0 or TMR1 Note: Refer to Figure 15-3 for load conditions.
TABLE 15-4:
Param No. Sym
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic Min Typ Max Units Conditions
40* 41* 42*
Tt0H Tt0L Tt0P
T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period
No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler
45*
Tt1H
46*
Tt1L
47*
Tt1P
T1CKI High Time Synchronous, Prescaler = 1 Synchronous, Standard(F) Prescaler = 2,4,8 Extended(LF) Asynchronous Standard(F) Extended(LF) T1CKI Low Time Synchronous, Prescaler = 1 Synchronous, Standard(F) Prescaler = 2,4,8 Extended(LF) Asynchronous Standard(F) Extended(LF) T1CKI input period Synchronous Standard(F)
Extended(LF)
Standard(F) -- -- ns Extended(LF) -- -- ns Ft1 Timer1 oscillator input frequency range -- 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc -- 7Tosc -- Legend: * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Asynchronous
0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0.5TCY + 20 15 25 30 50 0.5TCY + 20 15 25 30 50 Greater of: 30 OR TCY + 40 N Greater of: 50 OR TCY + 40 N 60 100 DC
-- -- -- -- -- --
-- -- -- -- -- --
ns ns ns ns ns ns
Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns
Must also meet parameter 47
N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8)
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PIC16F7X
FIGURE 15-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 52 51
RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 Note: Refer to Figure 15-3 for load conditions. 54
TABLE 15-5:
Param No. 50* Sym TccL
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Characteristic CCP1 and CCP2 input low time No Prescaler Standard(F) With Prescaler Extended(LF) Min 0.5TCY + 20 10 20 0.5TCY + 20 Standard(F) With Prescaler Extended(LF) 10 20 3TCY + 40 N Standard(F) Extended(LF) -- -- -- -- Typ Max Units -- -- -- -- -- -- -- 10 25 10 25 -- -- -- -- -- -- -- 25 50 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1,4 or 16) Conditions
51*
TccH
CCP1 and CCP2 input high time
No Prescaler
52* 53*
TccP TccR
CCP1 and CCP2 input period CCP1 and CCP2 output rise time
54*
TccF
CCP1 and CCP2 output fall time
Standard(F) Extended(LF)
Legend: * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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FIGURE 15-10: PARALLEL SLAVE PORT TIMING (PIC16F74/77 DEVICES ONLY)
RE2/CS
RE0/RD
RE1/WR
65 RD7:RD0 62 63 Note: Refer to Figure 15-3 for load conditions.
64
TABLE 15-6:
Parameter No. 62
PARALLEL SLAVE PORT REQUIREMENTS (PIC16F74/77 DEVICES ONLY)
Sym Characteristic Data in valid before WR or CS (setup time) Min Typ Max Units 20 25 -- -- -- -- -- -- -- -- -- -- -- 80 90 30 ns ns ns ns ns ns ns Extended Range Only Extended Range Only Conditions
TdtV2wrH
63*
TwrH2dtI
WR or CS to data in invalid (hold time) Standard(F) Extended(LF)
20 35 -- --
64
TrdL2dtV
RD and CS to data out valid
65
TrdH2dtI
RD or CS to data out invalid
10
Legend: * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC16F7X
FIGURE 15-11: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS 70 SCK (CKP = 0) 71 72
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb IN 74 73 Note: Refer to Figure 15-3 for load conditions. BIT6 - - - -1
BIT6 - - - - - -1
LSb
LSb IN
FIGURE 15-12: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79
SDO
MSb 75, 76
BIT6 - - - - - -1
LSb
SDI
MSb IN 74
BIT6 - - - -1
LSb IN
Note: Refer to Figure 15-3 for load conditions.
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FIGURE 15-13: SPI SLAVE MODE TIMING (CKE = 0)
SS 70 SCK (CKP = 0) 71 72 83
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb IN 74 73 Note: Refer to Figure 15-3 for load conditions. BIT6 - - - -1
BIT6 - - - - - -1
LSb 77 LSb IN
FIGURE 15-14: SPI SLAVE MODE TIMING (CKE = 1)
82 SS
SCK (CKP = 0)
70 83 71 72
SCK (CKP = 1) 80
SDO
MSb 75, 76
BIT6 - - - - - -1
LSb 77
SDI
MSb IN 74
BIT6 - - - -1
LSb IN
Note: Refer to Figure 15-3 for load conditions.
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TABLE 15-7:
Param No. 70* 71* 72* 73* 74* 75* 76* 77* 78* 79* 80* 81* 82* 83* Legend:
SPI MODE REQUIREMENTS
Characteristic SS to SCK or SCK input SCK input high time (Slave mode) SCK input low time (Slave mode) Setup time of SDI data input to SCK edge Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (Master mode) Standard(F) Extended(LF) SCK output fall time (Master mode) SDO data output valid after SCK Standard(F) edge Extended(LF) SDO data output setup to SCK edge SDO data output valid after SS edge Standard(F) Extended(LF) Min TCY TCY + 20 TCY + 20 100 100 -- -- -- 10 -- -- -- -- -- TCY -- Typ -- -- -- -- -- 10 25 10 -- 10 25 10 -- -- -- -- Max -- -- -- -- -- 25 50 25 50 25 50 25 50 145 -- 50 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions
Sym TssL2scH, TssL2scL TscH TscL TdiV2scH, TdiV2scL TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF TscH2doV, TscL2doV TdoV2scH, TdoV2scL TssL2doV
TscH2ssH, SS after SCK edge 1.5TCY + 40 -- -- ns TscL2ssH * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 15-15: I2C BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
START Condition Note: Refer to Figure 15-3 for load conditions.
STOP Condition
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TABLE 15-8:
Param No. 90* 91* 92* 93
I2C BUS START/STOP BITS REQUIREMENTS
Sym TSU:STA Characteristic START condition Setup time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min Typ Max Units 4700 -- 600 600 600 600 -- -- -- -- 4000 -- 4700 -- 4000 -- -- -- -- -- -- -- -- -- ns ns ns ns Conditions Only relevant for Repeated START condition After this period the first clock pulse is generated
THD:STA START condition Hold time TSU:STO STOP condition Setup time THD:STO STOP condition Hold time
* These parameters are characterized but not tested.
FIGURE 15-16: I2C BUS DATA TIMING
103 SCL 100 101 90 91 SDA In 110 109 SDA Out Note: Refer to Figure 15-3 for load conditions. 109 106 107 92 102
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TABLE 15-9:
Param. No. 100*
I2C BUS DATA REQUIREMENTS
Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module 100 kHz mode 400 kHz mode SSP Module 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4.0 0.6 1.5TCY 4.7 1.3 Max -- -- -- -- -- Units s s Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
Sym THIGH
101*
TLOW
Clock low time
s s
102*
TR
SDA and SCL rise time SDA and SCL fall time
-- 1.5TCY -- 1000 20 + 0.1Cb 300 -- 20 + 0.1Cb 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- --
ns ns ns ns s s s s ns s ns ns s s ns ns s s
Cb is specified to be from 10-400 pF Cb is specified to be from 10-400 pF Only relevant for Repeated START condition After this period the first clock pulse is generated
103*
TF
90* 91* 106* 107* 92* 109* 110*
TSU:STA START condition setup time THD:STA START condition hold time THD:DAT Data input hold time TSU:DAT Data input setup time TSU:STO STOP condition setup time TAA Output valid from clock TBUF Bus free time
(Note 2)
(Note 1) Time the bus must be free before a new transmission can start
Cb Bus capacitive loading -- 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast mode (400 kHz) I2C-bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement Tsu:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification), before the SCL line is released.
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FIGURE 15-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK Pin RC7/RX/DT Pin
121 121
120 122 Note: Refer to Figure 15-3 for load conditions.
TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param No. 120 Sym TckH2dtV Characteristic SYNC XMIT (MASTER & SLAVE) Clock high to data out valid Standard(F) -- Extended(LF) -- -- -- -- -- -- -- -- -- -- -- 80 100 45 50 45 50 ns ns ns ns ns ns Min Typ Max Units Conditions
121 122
Tckrf Tdtrf
Clock out rise time and fall time Standard(F) (Master mode) Extended(LF) Data out rise time and fall time Standard(F) Extended(LF)
: Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 15-18: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK pin RC7/RX/DT pin
125
126 Note: Refer to Figure 15-3 for load conditions.
TABLE 15-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter No. 125 126
:
Sym TdtV2ckL TckL2dtl
Characteristic SYNC RCV (MASTER & SLAVE) Data setup before CK (DT setup time) Data hold after CK (DT hold time)
Min
Typ
Max
Units Conditions
15 15
-- --
-- --
ns ns
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC16F7X
TABLE 15-12: A/D CONVERTER CHARACTERISTICS: PIC16F7X (INDUSTRIAL) PIC16LF7X (INDUSTRIAL)
Param Sym No. A01 NR Characteristic Resolution PIC16F7X PIC16LF7X A02 A03 A04 A05 A06 A10 A20 A25 A30 A40 EABS Total Absolute error EIL EDL EFS Integral linearity error Differential linearity error Full scale error Min -- -- -- -- -- -- -- -- 2.0V VSS - 0.3 -- -- -- 10 Typ -- -- -- -- -- -- -- guaranteed -- -- -- 180 90 -- Max 8 bits 8 bits <1 <1 <1 <1 <1 -- VDD + 0.3 VREF + 0.3 10.0 -- -- 1000 Units bit bit Conditions VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 2.0V
LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF -- V V k A A A Average current consumption when A/D is on (Note 1). During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 12.1. During A/D Conversion cycle. VSS VAIN VREF
EOFF Offset error -- Monotonicity (Note 3)
VREF Reference voltage VAIN Analog input voltage ZAIN Recommended impedance of analog voltage source IAD A/D conversion PIC16F7X current (VDD) PIC16LF7X
A50
IREF VREF input current (Note 2)
--
--
10
A
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
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FIGURE 15-19: A/D CONVERSION TIMING
BSF ADCON0, GO 134 Q4 130 A/D CLK 132 (TOSC/2)(1) 131 1 TCY
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO SAMPLING STOPPED DONE
SAMPLE
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 15-13: A/D CONVERSION REQUIREMENTS
Param Sym No. 130 Characteristic PIC16F7X PIC16LF7X PIC16F7X PIC16LF7X 131 132 TCNV Conversion time (not including S/H time) (Note 1) TACQ Acquisition time Min 1.6 2.0 2.0 3.0 9 5* Typ -- -- 4.0 6.0 -- -- Max -- -- 6.0 9.0 9 -- Units s s s s TAD s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Conditions TOSC based, VREF 3.0V TOSC based, 2.0V VREF 5.5V A/D RC mode A/D RC mode
TAD A/D clock period
134
TGO Q4 to A/D clock start
--
TOSC/2
--
--
135
TSWC Switching from convert sample time
1.5
--
--
TAD
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 12.1 for min. conditions.
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NOTES:
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16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at 25C. 'Max' or 'Min' represents (mean + 3) or (mean - 3), respectively, where is standard deviation over the whole temperature range. Graphs and Tables not available at this time.
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NOTES:
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17.0
17.1
PACKAGING INFORMATION
Package Marking Information
28-Lead PDIP (Skinny DIP) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example PIC16F77-I/SP 0017HAT
28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN
Example PIC16F76-I/SO 0010SAA
28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example PIC16F73-I/SS 0010SBP
Legend:
XX...X YY WW NNN
Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, and traceability code. For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
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PIC16F7X
Package Marking Information (Cont'd)
40-Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN
Example PIC16F77-I/P 0012SAA
44-Lead TQFP
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC16F77I/PT 0011HAT
44-Lead PLCC
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC16F77-I/L 0003SAT
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17.2 28-Lead Skinny Plastic Dual In-line (SP) - 300 mil (PDIP)
E1
D
2 n 1
E
A2 A L A1 B1 B p
c eB
Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN
INCHES* NOM 28 .100 .140 .125 .015 .300 .275 1.345 .125 .008 .040 .016 .320 5 5 .310 .285 1.365 .130 .012 .053 .019 .350 10 10 .325 .295 1.385 .135 .015 .065 .022 .430 15 15 .150 .130 .160 .135 MAX MIN
MILLIMETERS NOM 28 2.54 3.56 3.18 0.38 7.62 6.99 34.16 3.18 0.20 1.02 0.41 8.13 5 5 7.87 7.24 34.67 3.30 0.29 1.33 0.48 8.89 10 10 8.26 7.49 35.18 3.43 0.38 1.65 0.56 10.92 15 15 3.81 3.30 4.06 3.43 MAX
* Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070
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PIC16F7X
17.3 28-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E E1 p
D
B n h 45 c A Units Dimension Limits n p A A2 A1 E E1 D h L c B L A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 A2 2 1
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0
.104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15
2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052
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PIC16F7X
17.4 28-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
E E1 p
D
B n 2 1
A c A2
L
A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
.068 .064 .002 .299 .201 .396 .022 .004 0 .010 0 0
INCHES NOM 28 .026 .073 .068 .006 .309 .207 .402 .030 .007 4 .013 5 5
MAX
MIN
.078 .072 .010 .319 .212 .407 .037 .010 8 .015 10 10
MILLIMETERS* NOM MAX 28 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.10 5.11 5.25 5.38 10.06 10.20 10.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0.38 0 5 10 0 5 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073
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PIC16F7X
17.5 40-Lead Plastic Dual In-line (P) - 600 mil (PDIP)
E1
D
n E
2 1
A c eB Units Dimension Limits n p INCHES* NOM 40 .100 .175 .150 A1 B1 B p MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10
A2 L
MIN
MAX
MIN
MAX
Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .530 .545 .560 Overall Length D 2.045 2.058 2.065 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .030 .050 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .620 .650 .680 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016
4.83 4.06 15.88 14.22 52.45 3.43 0.38 1.78 0.56 17.27 15 15
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PIC16F7X
17.6 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E E1 #leads=n1 p
D1
D
B n
2 1
CH x 45 A
c
L A1 (F) Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH INCHES NOM 44 .031 11 .043 .039 .004 .024 .039 3.5 .472 .472 .394 .394 .006 .015 .035 10 10 MILLIMETERS* NOM 44 0.80 11 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.09 0.15 0.30 0.38 0.64 0.89 5 10 5 10 A2
MIN
MAX
MIN
MAX
Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.039 .037 .002 .018 0 .463 .463 .390 .390 .004 .012 .025 5 5
.047 .041 .006 .030 7 .482 .482 .398 .398 .008 .017 .045 15 15
1.20 1.05 0.15 0.75 7 12.25 12.25 10.10 10.10 0.20 0.44 1.14 15 15
Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076
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PIC16F7X
17.7 44-Lead Plastic Leaded Chip Carrier (L) - Square (PLCC)
E E1 #leads=n1
D1 D
n12 CH2 x 45 CH1 x 45 A3 A2
35
A B1 B p D2
c E2 Units Dimension Limits n p INCHES* NOM 44 .050 11 .165 .173 .145 .153 .020 .028 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .020 0 5 0 5
A1
MIN
MAX
MIN
Number of Pins Pitch Pins per Side n1 Overall Height A .180 Molded Package Thickness A2 .160 Standoff A1 .035 Side 1 Chamfer Height A3 .034 Corner Chamfer 1 CH1 .050 Corner Chamfer (others) CH2 .010 Overall Width E .695 Overall Length D .695 Molded Package Width E1 .656 Molded Package Length D1 .656 Footprint Width E2 .630 Footprint Length D2 .630 c Lead Thickness .013 Upper Lead Width B1 .032 B .021 Lower Lead Width Mold Draft Angle Top 10 Mold Draft Angle Bottom 10 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-048
MILLIMETERS NOM 44 1.27 11 4.19 4.39 3.68 3.87 0.51 0.71 0.61 0.74 1.02 1.14 0.00 0.13 17.40 17.53 17.40 17.53 16.51 16.59 16.51 16.59 14.99 15.75 14.99 15.75 0.20 0.27 0.66 0.74 0.33 0.51 0 5 0 5
MAX
4.57 4.06 0.89 0.86 1.27 0.25 17.65 17.65 16.66 16.66 16.00 16.00 0.33 0.81 0.53 10 10
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PIC16F7X
APPENDIX A:
Version A
REVISION HISTORY
Date 2000 Revision Description This is a new data sheet. However, these devices are similar to the PIC16C7X devices found in the PIC16C7X Data Sheet (DS30390) or the PIC16F87X devices (DS30292).
APPENDIX B:
DEVICE DIFFERENCES
The differences between the devices in this data sheet are listed in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
PIC16F76/73 5 channels, 8-bits no 28-pin PDIP, 28-pin SOIC, 28-pin SSOP PIC16F77/74 8 channels, 8-bits yes 40-pin PDIP, 44-pin TQFP, 44-pin PLCC
Difference A/D Parallel Slave Port Packages
APPENDIX C:
CONVERSION CONSIDERATIONS
Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.
TABLE C-1:
CONVERSION CONSIDERATIONS
PIC16C7X 28/40 3 11 or 12 PSP, USART, SSP (SPI, I2C Slave) 20 MHz 8-bit 2 4K, 8K EPROM 192, 368 bytes None -- 28/40 3 13 or 14 PSP, USART, SSP (SPI, I2C Master/Slave) 20 MHz 10-bit 2 4K, 8K FLASH (1,000 E/W cycles) 192, 368 bytes 128, 256 bytes In-Circuit Debugger, Low Voltage Programming PIC16F87X 28/40 3 11 or 12 PSP, USART, SSP (SPI, I2C Slave) 20 MHz 8-bit 2 4K, 8K FLASH (100 E/W cycles) 192, 368 bytes None -- PIC16F7X
Characteristic Pins Timers Interrupts Communication Frequency A/D CCP Program Memory RAM EEPROM Data Other
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NOTES:
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PIC16F7X
INDEX A
A/D ..................................................................................... 89 ADCON0 Register ...................................................... 89 ADCON1 Register ...................................................... 90 Analog Input Model Block Diagram ............................ 92 Analog Port Pins ...................................... 7, 8, 9, 37, 38 Analog-to-Digital Converter ........................................ 89 Block Diagram ............................................................ 91 Configuring Analog Port Pins ..................................... 93 Configuring the Interrupt ............................................ 91 Configuring the Module .............................................. 91 Conversion Clock ....................................................... 93 Conversions ............................................................... 93 Converter Characteristics ........................................ 144 Effects of a RESET .................................................... 93 Faster Conversion - Lower Resolution Tradeoff ........ 93 Internal Sampling Switch (Rss) Impedance ............... 92 Operation During SLEEP ........................................... 93 Sampling Requirements ............................................. 92 Source Impedance ..................................................... 92 Timing Diagram ........................................................ 145 Using the CCP Trigger ............................................... 93 Absolute Maximum Ratings ............................................. 125 ACK .............................................................................. 67, 69 ADRES Register .......................................................... 15, 89 Analog Port Pins. See A/D Application Notes AN552 (Implementing Wake-up on Key Strokes Using PIC16F7X) ................................................................. 31 AN556 (Table Reading Using PIC16CXX .................. 26 AN578 (Use of the SSP Module in the I2C Multi-Master Environment) .............................................................. 61 Architecture PIC16F73/PIC16F76 Block Diagram ........................... 5 PIC16F74/PIC16F77 Block Diagram ........................... 6 Assembler MPASM Assembler .................................................. 119 CCP1IF .............................................................. 57 Mode ................................................................. 57 Prescaler ........................................................... 57 CCP Timer Resources ............................................... 55 Compare Block Diagram ................................................... 58 Mode ................................................................. 58 Software Interrupt Mode .................................... 58 Special Event Trigger ........................................ 58 Special Trigger Output of CCP1 ........................ 58 Special Trigger Output of CCP2 ........................ 58 Interaction of Two CCP Modules ............................... 55 Section ....................................................................... 55 Special Event Trigger and A/D Conversions ............. 58 Capture/Compare/PWM (CCP) CCP1 RC2/CCP1 Pin ................................................. 7, 8 CCP2 RC1/T1OSI/CCP2 Pin ..................................... 7, 8 PWM Block Diagram ................................................. 58 PWM Mode ................................................................ 58 CCP1CON ......................................................................... 17 CCP2CON ......................................................................... 17 CCPR1H Register .................................................. 15, 17, 55 CCPR1L Register ........................................................ 17, 55 CCPR2H Register ........................................................ 15, 17 CCPR2L Register ........................................................ 15, 17 CCPxM0 bit ........................................................................ 56 CCPxM1 bit ........................................................................ 56 CCPxM2 bit ........................................................................ 56 CCPxM3 bit ........................................................................ 56 CCPxX bit .......................................................................... 56 CCPxY bit .......................................................................... 56 CKE ................................................................................... 62 CKP ................................................................................... 63 Clock Polarity Select bit, CKP ............................................ 63 Code Examples Call of a Subroutine in Page 1 from Page 0 .............. 26 Indirect Addressing .................................................... 27 Code Protection ......................................................... 95, 110 Computed GOTO ............................................................... 26 Configuration Bits .............................................................. 95 Conversion Considerations .............................................. 157
B
Banking, Data Memory ...................................................... 12 BF ................................................................................ 62, 67 Block Diagrams A/D ............................................................................. 91 Analog Input Model .................................................... 92 Capture ...................................................................... 57 Compare .................................................................... 58 I2C Mode .................................................................... 67 PWM .......................................................................... 58 SSP in I2C Mode ........................................................ 67 SSP in SPI Mode ....................................................... 64 Timer0/WDT Prescaler .............................................. 45 Timer2 ........................................................................ 53 USART Receive ......................................................... 79 USART Transmit ........................................................ 77 BOR. See Brown-out Reset BRGH bit ............................................................................ 75 Brown-out Reset (BOR) ............................... 95, 99, 101, 102 Buffer Full Status bit, BF .................................................... 62
D
D/A ..................................................................................... 62 Data Memory ..................................................................... 12 Bank Select (RP1:RP0 Bits) ...................................... 12 General Purpose Registers ....................................... 12 Register File Map ................................................ 13, 14 Special Function Registers ........................................ 15 Data/Address bit, D/A ........................................................ 62 DC Characteristics ........................................................... 127 Development Support ...................................................... 119 Device Differences ........................................................... 157 Device Overview .................................................................. 5 Direct Addressing .............................................................. 27
E
Electrical Characteristics ................................................. 125 Errata ................................................................................... 4 External Clock Input (RA4/T0CKI). See Timer0 External Interrupt Input (RB0/INT). See Interrupt Sources
C
Capture/Compare/PWM Capture Block Diagram ................................................... 57 CCP1CON Register ........................................... 56
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F
Firmware Instructions ....................................................... 111 FSR Register .................................................... 15, 16, 17, 27 Summary Table ....................................................... 112 INT Interrupt (RB0/INT). See Interrupt Sources INTCON ............................................................................. 17 INTCON Register ............................................................... 20 GIE Bit ....................................................................... 20 INTE Bit ......................................................... 20, 21, 22 INTF Bit ..................................................................... 20 RBIF Bit ......................................................... 20, 21, 31 T0IE Bit ...................................................................... 20 Internal Sampling Switch (Rss) Impedance ....................... 92 Interrupt Sources ....................................................... 95, 105 Block Diagram ......................................................... 105 Interrupt on Change (RB7:RB4 ) ............................... 31 RB0/INT Pin, External ...................................... 7, 8, 106 TMR0 Overflow ........................................................ 106 USART Receive/Transmit Complete ......................... 73 Interrupts Synchronous Serial Port Interrupt .............................. 22 Interrupts, Context Saving During .................................... 106 Interrupts, Enable Bits Global Interrupt Enable (GIE Bit) ....................... 20, 105 Interrupt on Change (RB7:RB4) Enable (RBIE Bit) . 106 RB0/INT Enable (INTE Bit) ............................ 20, 21, 22 TMR0 Overflow Enable (T0IE Bit) ............................. 20 Interrupts, Flag Bits Interrupt on Change (RB7:RB4) Flag (RBIF Bit) . 20, 21, 31, 106 RB0/INT Flag (INTF Bit) ............................................ 20 TMR0 Overflow Flag (T0IF Bit) ................................ 106
I
I/O Ports ............................................................................. 29 I2C Addressing ................................................................. 68 Block Diagram ............................................................ 67 I2C Operation ............................................................. 67 Master Mode .............................................................. 71 Mode .......................................................................... 67 Mode Selection .......................................................... 67 Multi-Master Mode ..................................................... 71 Reception ................................................................... 69 Reception Timing Diagram ........................................ 69 SCL and SDA pins ..................................................... 67 Slave Mode ................................................................ 67 Transmission .............................................................. 70 I2C (SSP Module) Timing Diagram, Data .............................................. 141 Timing Diagram, Start/Stop Bits ............................... 140 ID Locations ............................................................... 95, 110 In-Circuit Serial Programming (ICSP) ........................ 95, 110 INDF ................................................................................... 17 INDF Register ........................................................ 15, 16, 27 Indirect Addressing ............................................................ 27 FSR Register ............................................................. 12 Instruction Format ............................................................ 111 Instruction Set .................................................................. 111 ADDLW .................................................................... 113 ADDWF .................................................................... 113 ANDLW .................................................................... 113 ANDWF .................................................................... 113 BCF .......................................................................... 113 BSF .......................................................................... 113 BTFSC ..................................................................... 114 BTFSS ..................................................................... 114 CALL ........................................................................ 114 CLRF ........................................................................ 114 CLRW ...................................................................... 114 CLRWDT .................................................................. 114 COMF ...................................................................... 115 DECF ....................................................................... 115 DECFSZ ................................................................... 115 GOTO ...................................................................... 115 INCF ......................................................................... 115 INCFSZ .................................................................... 115 IORLW ..................................................................... 116 IORWF ..................................................................... 116 MOVF ....................................................................... 116 MOVLW ................................................................... 116 MOVWF ................................................................... 116 NOP ......................................................................... 116 RETFIE .................................................................... 117 RETLW .................................................................... 117 RETURN .................................................................. 117 RLF .......................................................................... 117 RRF .......................................................................... 117 SLEEP ..................................................................... 117 SUBLW .................................................................... 118 SUBWF .................................................................... 118 SWAPF .................................................................... 118 XORLW .................................................................... 118 XORWF .................................................................... 118
K
KeeLoq Evaluation and Programming Tools ................ 122
L
Loading of PC .................................................................... 26
M
Master Clear (MCLR) ....................................................... 7, 8 MCLR Reset, Normal Operation ................ 99, 101, 102 MCLR Reset, SLEEP ................................. 99, 101, 102 Memory Organization Data Memory ............................................................. 12 Program Memory ....................................................... 11 MPLAB Integrated Development Environment Software . 119
O
OPCODE Field Descriptions ............................................ 111 OPTION ............................................................................. 17 OPTION_REG Register ..................................................... 19 INTEDG Bit ................................................................ 19 PS2:PS0 Bits ............................................................. 19 PSA Bit ................................................................ 19, 20 RBPU Bit ................................................................... 19 T0CS Bit .................................................................... 19 T0SE Bit .................................................................... 19 OSC1/CLKIN Pin ............................................................. 7, 8 OSC2/CLKOUT Pin ......................................................... 7, 8 Oscillator Configuration ............................................... 95, 97 HS ...................................................................... 97, 101 LP ...................................................................... 97, 101 RC ............................................................... 97, 98, 101 XT ...................................................................... 97, 101 Oscillator, WDT ................................................................ 107 Output of TMR2 ................................................................. 53
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P
P ......................................................................................... 62 Packaging ........................................................................ 149 Paging, Program Memory ............................................ 11, 26 Parallel Slave Port (PSP) ......................................... 9, 34, 38 Block Diagram ............................................................ 38 RE0/RD/AN5 Pin .............................................. 9, 37, 38 RE1/WR/AN6 Pin ............................................. 9, 37, 38 RE2/CS/AN7 Pin .............................................. 9, 37, 38 Read Waveforms ....................................................... 39 Select (PSPMODE Bit) .................................. 34, 35, 38 Write Waveforms ....................................................... 39 PCFG0 bit .......................................................................... 90 PCFG1 bit .......................................................................... 90 PCFG2 bit .......................................................................... 90 PCL Register .................................................... 15, 16, 17, 26 PCLATH Register ............................................ 15, 16, 17, 26 PCON Register .................................................... 17, 25, 100 POR Bit ...................................................................... 25 PIC16F76 Pinout Description ............................................... 7 PICDEM-1 Low-Cost PICmicro Demo Board ................... 121 PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 121 PICDEM-3 Low-Cost PIC16CXXX Demo Board .............. 121 PICSTART Plus Entry Level Development System ...... 121 PIE1 Register ............................................................... 17, 21 PIE2 Register ............................................................... 17, 23 Pinout Descriptions PIC16F73/PIC16F76 .................................................... 7 PIC16F74/PIC16F77 .................................................... 8 PIR1 Register ..................................................................... 22 PIR2 Register ..................................................................... 24 POP ................................................................................... 26 POR. See Power-on Reset PORTA ....................................................................... 7, 8, 17 Analog Port Pins ...................................................... 7, 8 Initialization ................................................................ 29 PORTA Register ........................................................ 29 RA3 RA0 and RA5 Port Pins ..................................... 29 RA4/T0CKI Pin ................................................... 7, 8, 29 RA5/SS/AN4 Pin ...................................................... 7, 8 TRISA Register .......................................................... 29 PORTA Register ................................................................ 15 PORTB ....................................................................... 7, 8, 17 PORTB Register ........................................................ 31 Pull-up Enable (RBPU Bit) ......................................... 19 RB0/INT Edge Select (INTEDG Bit) ........................... 19 RB0/INT Pin, External ...................................... 7, 8, 106 RB3:RB0 Port Pins .................................................... 31 RB7:RB4 Interrupt on Change ................................. 106 RB7:RB4 Interrupt on Change Enable (RBIE Bit) .... 106 RB7:RB4 Interrupt on Change Flag (RBIF Bit) ... 20, 21, 31, 106 RB7:RB4 Port Pins .................................................... 31 TRISB Register .......................................................... 31 PORTB Register ................................................................ 15 PORTC ...................................................................... 7, 8, 17 Block Diagram ............................................................ 33 PORTC Register ........................................................ 33 RC0/T1OSO/T1CKI Pin ........................................... 7, 8 RC1/T1OSI/CCP2 Pin .............................................. 7, 8 RC2/CCP1 Pin ......................................................... 7, 8 RC3/SCK/SCL Pin ................................................... 7, 8 RC4/SDI/SDA Pin .................................................... 7, 8 RC5/SDO Pin ........................................................... 7, 8 RC6/TX/CK Pin .................................................. 7, 8, 74 RC7/RX/DT Pin ........................................... 7, 8, 74, 75 TRISC Register ................................................... 33, 73 PORTC Register ................................................................ 15 PORTD .................................................................... 9, 17, 38 Block Diagram ........................................................... 34 Parallel Slave Port (PSP) Function ............................ 34 PORTD Register ........................................................ 34 TRISD Register ......................................................... 34 PORTD Register ................................................................ 15 PORTE .......................................................................... 9, 17 Analog Port Pins .............................................. 9, 37, 38 Block Diagram ........................................................... 35 Input Buffer Full Status (IBF Bit) ................................ 36 Input Buffer Overflow (IBOV Bit) ................................ 36 PORTE Register ........................................................ 35 PSP Mode Select (PSPMODE Bit) ................ 34, 35, 38 RE0/RD/AN5 Pin ............................................. 9, 37, 38 RE1/WR/AN6 Pin ............................................ 9, 37, 38 RE2/CS/AN7 Pin ............................................. 9, 37, 38 TRISE Register .......................................................... 35 PORTE Register ................................................................ 15 Postscaler, WDT Assignment (PSA Bit) .......................................... 19, 20 Rate Select (PS2:PS0 Bits) ....................................... 19 Power-down Mode. See SLEEP Power-on Reset (POR) ........................ 95, 99, 100, 101, 102 Oscillator Start-up Timer (OST) ......................... 95, 100 POR Status (POR Bit) ............................................... 25 Power Control (PCON) Register .............................. 100 Power-down (PD Bit) ................................................. 99 Power-up Timer (PWRT) ................................... 95, 100 Time-out (TO Bit) ................................................. 18, 99 Time-out Sequence on Power-up .................... 103, 104 PR2 .................................................................................... 17 PR2 Register ............................................................... 16, 53 Prescaler, Timer0 Assignment (PSA Bit) .......................................... 19, 20 Rate Select (PS2:PS0 Bits) ....................................... 19 PRO MATE II Universal Programmer ........................... 121 Program Counter Reset Conditions ..................................................... 101 Program Memory ............................................................... 11 Interrupt Vector .......................................................... 11 Paging ................................................................. 11, 26 Program Memory Map ............................................... 11 Reset Vector .............................................................. 11 Program Verification ........................................................ 110 Programming Pin (Vpp) ................................................... 7, 8 Programming, Device Instructions ................................... 111 PUSH ................................................................................. 26
R
R/W .................................................................................... 62 R/W bit ................................................................... 68, 69, 70 RAM. See Data Memory RCREG .............................................................................. 17 RCSTA Register .......................................................... 17, 74 OERR Bit ................................................................... 74 SPEN Bit .................................................................... 73 SREN Bit ................................................................... 74 Read/Write bit Information, R/W ........................................ 62 Receive Overflow Indicator bit, SSPOV ............................. 63 Register File ....................................................................... 12 Register File Map ......................................................... 13, 14
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PIC16F7X
Registers FSR Summary ............................................................ 17 INDF Summary ............................................................ 17 INTCON Summary ............................................................ 17 OPTION Summary ............................................................ 17 PCL Summary ............................................................ 17 PCLATH Summary ............................................................ 17 PORTB Summary ............................................................ 17 SSPSTAT ................................................................... 62 STATUS Summary ............................................................ 17 Summary .................................................................... 15 TMR0 Summary ............................................................ 17 TRISB Summary ............................................................ 17 RESET ......................................................................... 95, 99 Reset Block Diagram ............................................................ 99 Brown-out Reset (BOR). See Brown-out Reset (BOR) MCLR Reset. See MCLR Power-on Reset (POR). See Power-on Reset (POR) Reset Conditions for All Registers ........................... 102 Reset Conditions for PCON Register ....................... 101 Reset Conditions for Program Counter .................... 101 Reset Conditions for STATUS Register ................... 101 WDT Reset. See Watchdog Timer (WDT) Revision History ............................................................... 157 SPI Clock Edge Select bit, CKE ........................................ 62 SPI Data Input Sample Phase Select bit, SMP ................. 62 SSP Module Overview ....................................................... 61 RA5/SS/AN4 Pin ...................................................... 7, 8 RC3/SCK/SCL Pin ................................................... 7, 8 RC4/SDI/SDA Pin .................................................... 7, 8 RC5/SDO Pin ........................................................... 7, 8 Section ....................................................................... 61 SSPCON ................................................................... 63 SSPSTAT .................................................................. 62 SSPADD Register .............................................................. 17 SSPBUF ............................................................................ 17 SSPBUF Register .............................................................. 15 SSPCON ............................................................................ 63 SSPCON Register ............................................................. 15 SSPEN ............................................................................... 63 SSPIF ................................................................................ 22 SSPM3:SSPM0 ................................................................. 63 SSPOV ........................................................................ 63, 67 SSPSTAT Register ................................................ 16, 17, 62 Stack .................................................................................. 26 Overflows ................................................................... 26 Underflow .................................................................. 26 Start bit, S .......................................................................... 62 STATUS Register ........................................................ 17, 18 DC Bit .................................................................. 18, 36 IRP Bit ....................................................................... 18 PD Bit ........................................................................ 99 TO Bit .................................................................. 18, 99 Z Bit ..................................................................... 18, 36 Stop bit, P .......................................................................... 62 Synchronous Serial Port Enable bit, SSPEN ..................... 63 Synchronous Serial Port Interrupt ...................................... 22 Synchronous Serial Port Mode Select bits, SSPM3:SSPM0 . 63 Synchronous Serial Port Module ....................................... 61 Synchronous Serial Port Status Register .......................... 62
S
S ......................................................................................... 62 SCI. See USART SCL .................................................................................... 67 Serial Communication Interface. See USART Slave Mode SCL ............................................................................ 67 SDA ............................................................................ 67 SLEEP .................................................................. 95, 99, 108 SMP ................................................................................... 62 Software Simulator (MPLAB-SIM) .................................... 120 SPBRG ............................................................................... 17 SPBRG Register ................................................................ 16 Special Features of the CPU .............................................. 95 Special Function Registers ................................................ 15 PIC16F73 ................................................................... 15 PIC16F74 ................................................................... 15 Speed, Operating ................................................................. 1 SPI Block Diagram ............................................................ 64 Master Mode Timing .................................................. 65 Serial Clock ................................................................ 61 Serial Data In ............................................................. 61 Serial Data Out .......................................................... 61 Slave Mode Timing .................................................... 65 Slave Mode Timing Diagram ...................................... 65 Slave Select ............................................................... 61 SPI Mode ................................................................... 61 SSPCON .................................................................... 63 SSPSTAT ................................................................... 62
T
T1CKPS0 bit ...................................................................... 49 T1CKPS1 bit ...................................................................... 49 T1CON ............................................................................... 17 T1CON Register .......................................................... 17, 49 T1OSCEN bit ..................................................................... 49 T1SYNC bit ........................................................................ 49 T2CKPS0 bit ...................................................................... 53 T2CKPS1 bit ...................................................................... 53 T2CON Register .......................................................... 17, 53 TAD ..................................................................................... 93 Timer0 Clock Source Edge Select (T0SE Bit) ....................... 19 Clock Source Select (T0CS Bit) ................................. 19 Overflow Enable (T0IE Bit) ........................................ 20 Overflow Flag (T0IF Bit) ........................................... 106 Overflow Interrupt .................................................... 106 RA4/T0CKI Pin, External Clock ............................... 7, 8 Timer1 ................................................................................ 49 RC0/T1OSO/T1CKI Pin ........................................... 7, 8 RC1/T1OSI/CCP2 Pin ............................................. 7, 8 Timers Timer0 External Clock ................................................... 46 Interrupt ............................................................. 45 Prescaler ........................................................... 46 Prescaler Block Diagram ................................... 45
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Section ............................................................... 45 T0CKI ................................................................. 46 Timer1 Asynchronous Counter Mode ............................ 51 Capacitor Selection ............................................ 51 Operation in Timer Mode ................................... 50 Oscillator ............................................................ 51 Prescaler ............................................................ 51 Resetting of Timer1 Registers ........................... 51 Resetting Timer1 using a CCP Trigger Output .. 51 Synchronized Counter Mode ............................. 50 T1CON ............................................................... 49 TMR1H .............................................................. 51 TMR1L ............................................................... 51 Timer2 Block Diagram ................................................... 53 Postscaler .......................................................... 53 Prescaler ............................................................ 53 T2CON ............................................................... 53 Timing Diagrams Brown-out Reset ...................................................... 134 Capture/Compare/PWM ........................................... 136 CLKOUT and I/O ...................................................... 133 I2C Reception (7-bit Address) .................................... 69 Power-up Timer ....................................................... 134 Reset ........................................................................ 134 SPI Master Mode ....................................................... 65 SPI Slave Mode (CKE = 1) ........................................ 65 SPI Slave Mode Timing (CKE = 0) ............................ 65 Start-up Timer .......................................................... 134 Time-out Sequence on Power-up .................... 103, 104 Timer0 ...................................................................... 135 Timer1 ...................................................................... 135 USART Asynchronous Master Transmission ............. 78 USART Asynchronous Reception .............................. 79 USART Synchronous Receive ................................. 143 USART Synchronous Reception ................................ 85 USART Synchronous Transmission .................. 83, 143 Wake-up from SLEEP via Interrupt .......................... 109 Watchdog Timer ....................................................... 134 Timing Diagrams and Specifications A/D Conversion ........................................................ 145 I2C Bus Data ............................................................ 141 I2C Bus Start/Stop Bits ............................................. 140 TMR0 ................................................................................. 17 TMR0 Register ................................................................... 15 TMR1CS bit ....................................................................... 49 TMR1H ............................................................................... 17 TMR1H Register ................................................................ 15 TMR1L ............................................................................... 17 TMR1L Register ................................................................. 15 TMR1ON bit ....................................................................... 49 TMR2 ................................................................................. 17 TMR2 Register ................................................................... 15 TMR2ON bit ....................................................................... 53 TOUTPS0 bit ...................................................................... 53 TOUTPS1 bit ...................................................................... 53 TOUTPS2 bit ...................................................................... 53 TOUTPS3 bit ...................................................................... 53 TRISA ................................................................................ 17 TRISA Register .................................................................. 16 TRISB ................................................................................ 17 TRISB Register .................................................................. 16 TRISC ................................................................................ 17 TRISC Register .................................................................. 16 TRISD ................................................................................ 17 TRISD Register .................................................................. 16 TRISE ................................................................................ 17 TRISE Register ............................................................ 16, 35 IBF Bit ........................................................................ 36 IBOV Bit ..................................................................... 36 PSPMODE Bit ............................................... 34, 35, 38 TXREG .............................................................................. 17 TXSTA ............................................................................... 17 TXSTA Register ................................................................. 73 SYNC Bit ............................................................. 73, 74 TRMT Bit ................................................................... 73 TX9 Bit ....................................................................... 73 TX9D Bit .................................................................... 73 TXEN Bit .............................................................. 73, 89
U
UA ...................................................................................... 62 Universal Synchronous Asynchronous Receiver Transmitter. See USART Update Address bit, UA ..................................................... 62 USART .............................................................................. 73 Asynchronous Mode .................................................. 77 Receive Block Diagram ..................................... 81 Asynchronous Receiver ............................................. 79 Asynchronous Reception ........................................... 80 Asynchronous Transmitter ......................................... 77 Baud Rate Generator (BRG) ..................................... 75 Baud Rate Formula ........................................... 75 Baud Rates, Asynchronous Mode (BRGH=0) ... 76 Sampling ........................................................... 75 Mode Select (SYNC Bit) ...................................... 73, 74 Overrun Error (OERR Bit) .......................................... 74 RC6/TX/CK Pin ........................................................ 7, 8 RC7/RX/DT Pin ....................................................... 7, 8 RCSTA Register ........................................................ 74 Receive Block Diagram ............................................. 79 Serial Port Enable (SPEN Bit) ................................... 73 Single Receive Enable (SREN Bit) ............................ 74 Synchronous Master Mode ........................................ 82 Synchronous Master Reception ................................ 84 Synchronous Master Transmission ........................... 82 Synchronous Slave Mode .......................................... 86 Transmit Block Diagram ............................................ 77 Transmit Data, 9th Bit (TX9D) ................................... 73 Transmit Enable (TXEN Bit) ................................ 73, 89 Transmit Enable, Nine-bit (TX9 Bit) ........................... 73 Transmit Shift Register Status (TRMT Bit) ................ 73 TXSTA Register ......................................................... 73
W
Wake-up from SLEEP ................................................ 95, 108 Interrupts ......................................................... 101, 102 MCLR Reset ............................................................ 102 Timing Diagram ....................................................... 109 WDT Reset .............................................................. 102 Watchdog Timer (WDT) ............................................. 95, 107 Block Diagram ......................................................... 107 Enable (WDTE Bit) .................................................. 107 Postscaler. See Postscaler, WDT Programming Considerations .................................. 107 RC Oscillator ........................................................... 107 Time-out Period ....................................................... 107 WDT Reset, Normal Operation .................. 99, 101, 102 WDT Reset, SLEEP .................................. 99, 101, 102 WCOL ................................................................................ 63
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PIC16F7X
Write Collision Detect bit, WCOL ....................................... 63 WWW, On-Line Support ....................................................... 4
DS30325A-page 164
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PIC16F7X
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-786-7302 for the rest of the world.
000815
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
Trademarks: The Microchip name, logo, PIC, PICmicro, PICSTART, PICMASTER, PRO MATE and MPLAB are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM, microID and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies.
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PIC16F7X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16F7X Questions: 1. What are the best features of this document? Y N Literature Number: DS30325A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30325A-page 166
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PIC16F7X
PIC16F7X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device PIC16F7X(1), PIC16F7XT(1); VDD range 4.0V to 5.5V PIC16LF7X(1), PIC16LF7XT(1); VDD range 2.0V to 5.5V c) PIC16F77-I/P 301 = Commercial temp., PDIP package, normal VDD limits, QTP pattern #301. PIC16LF76-I/SO = Industrial temp., SOIC package, 200 kHz, Extended VDD limits. PIC16F74-I/P = Industrial temp., PDIP package, normal VDD limits.
Temperature Range
I
= -40C to
+85C
(Industrial) Note 1: F LF T = CMOS FLASH = Low Power CMOS FLASH = in tape and reel - SOIC, PLCC, SSOP, TQFP packages only.
Package
PT SO SP P L SS
= = = = = =
TQFP (Thin Quad Flatpack) SOIC Skinny plastic dip PDIP PLCC SSOP
Pattern
QTP, SQTP, Code or Special Requirements (blank otherwise)
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
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DS30325A-page 167
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com
ASIA/PACIFIC
China - Beijing
Microchip Technology Beijing Office Unit 915 New China Hong Kong Manhattan Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850
Rocky Mountain
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Taiwan
Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
China - Shanghai
Microchip Technology Shanghai Office Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Atlanta
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EUROPE
Denmark
Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
Boston
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Germany
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Japan
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Detroit
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Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
Korea
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Los Angeles
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United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
9/01/00
New York
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San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Toronto
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Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
All rights reserved. (c) 2001 Microchip Technology Incorporated. Printed in the USA. 3/01
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
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1.0 Device Overview............................................................................................................................................................ 5 2.0 Memory Organization .................................................................................................................................................. 11 3.0 I/O Ports....................................................................................................................................................................... 29 4.0 Reading Program Memory........................................................................................................................................... 41 5.0 Timer0 Module............................................................................................................................................................. 45 6.0 Timer1 Module............................................................................................................................................................. 49 7.0 Timer2 Module............................................................................................................................................................. 53 8.0 Capture/Compare/PWM Modules................................................................................................................................ 55 9.0 Synchronous Serial Port (SSP) Module....................................................................................................................... 61 10.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ...................................................................... 73 11.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................... 89 12.0 Special Features of the CPU ....................................................................................................................................... 95 13.0 Instruction Set Summary ........................................................................................................................................... 111 14.0 Development Support ................................................................................................................................................ 119 15.0 Electrical Characteristics ........................................................................................................................................... 125 16.0 DC and AC Characteristics Graphs and Tables ........................................................................................................ 147 17.0 Packaging Information ............................................................................................................................................... 149 Revision History 157 Device Differences 157 Conversion Considerations 157 ................................................................................................................................................................................. On-Line Support165 *............................................................................................................................................................................. Reader Response166 ........................................................................................................................................... PIC16F7X Product Identification System167
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